Abstract: The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved.

Abstract: The present invention provides a data processing apparatus and method for predicting instructions in a data processing apparatus. The data processing apparatus comprises a processor core for executing instructions from any of a plurality of instruction sets, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor core for execution. Further, prediction logic is used to predict which instructions should be prefetched by the prefetch unit, the prediction logic being arranged to review a prefetched instruction to predict whether execution of that prefetched instruction will cause a change in instruction flow, and if so to indicate to the prefetch unit an address within the memory from which a next instruction should be retrieved.

Abstract: A data processing apparatus and method is provided for applying a floating-point multiply-accumulate operation to first, second and third operands. The apparatus comprises a multiplier for multiplying the second and third operands and applying rounding to produce a rounded multiplication result, and an adder for adding the rounded multiplication result to the first operand to generate a final result and for applying rounding to generate a rounded final result. Further, control logic is provided which is responsive to a first single instruction to control the multiplier and adder to cause the rounded final result generated by the adder to be equivalent to the subtraction of the rounded multiplication result from the first operand.

Abstract: Apparatus for processing data is provided, said apparatus comprising: a main processor 4 responsive to main processor instructions within a stream of instructions input to said main processor 4 to perform main processor operations; a coprocessor 6 coupled to said main processor 4 via a coprocessor interface CP and responsive to coprocessor instructions MCR, MRC within said stream of instructions to perform coprocessor operations; wherein said coprocessor 6 is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor. Using a debug mechanism in the form of a debug coprocessor reduces the impact of the debug mechanism upon normal operation.

Abstract: A data processing apparatus and method is provided for performing a multiply-accumulate operation A+(B*C) in response to a single instruction identifying said multiply-accumulate operation. The data processing operation comprises a multiplier for multiplying values B and C to generate an unrounded multiplication result, the multiplier further being arranged to generate first data required for rounding determination, and an adder for adding the unrounded multiplication result to a value A to generate an unrounded multiply-accumulate result, the adder further being arranged to generate second data required for rounding determination. Determination logic is then provided for using the first and second data to determine one or more rounding values required to produce a final multiply-accumulate result equivalent to the execution of a separate multiply instruction incorporating rounding, followed by a separate add instruction incorporating rounding.

Abstract: Apparatus for processing data is provided, said apparatus comprising: a main processor 4; an instruction transfer register ITR for holding a data processing instruction and accessible via a first serial scan chain SC4; a data transfer register DTR for holding a data value and accessible via a second serial scan chain SC5; debug logic 6, 12 for controlling said main processor 4, said instruction transfer register ITR and said data transfer register DTR such that a data processing instruction held within said instruction transfer register ITR is passed a plurality of times to said main processor 4 for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain. In this way operational speed of the debug mode is increased since the data processing instruction only needs to be transferred once.

Abstract: Apparatus for processing data is provided, said apparatus comprising: a main processor 4 driven by a main processor clock signal clk at a main processor clock frequency; debug logic 6, 12 at least a portion 12 of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic 12 and from which said data processing instruction may be read by said main processor 4; wherein when switched from a normal mode to a debug mode said main processor 4 continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic 12 triggers said main processor to read and execute said data

Abstract: A floating point unit is provided with a register bank comprising 32 registers that may be used as either vector registers of scalar registers. A data processing instruction includes at least one register specifying field pointing to a register containing a data value to be used in that operation. An increase in the instruction bit space available to encode more opcodes or to allow for more registers is provided by encoding whether a register is to be treated as a vector or a scalar within the register field itself. Further, the register field for one register of the instruction may encode whether another register is a vector or a scalar. The registers can be initially accessed using the values within the register fields of the instruction independently of the opcode allowing for easier decode.

Abstract: A data processing system having a main processor and a coprocessor. The main processor responsds to coprocessor instructions within its instruction stream by issuing the coprocessor instructions upon a coprocessor bus and detecting if the coprocessor accepts them by returning an accept signal. The coprocessor instructions include a coprocessor number and the coprocessor checks this number to see if it matches its own number(s) to determine whether or not it should accept the coprocessor instruction. A data type field within the coprocessor number in the coprocessor instruction also serves to specify one of multiple data types to be used in the coprocessor operation; particular coprocessors can interpret this part of the coprocessor number to determine data type. If the coprocessor supports multiple data types, then it has multiple coprocessor numbers for which it will issue accept signals and then uses the data type field to control the data type used.

Abstract: A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of ‘n’ instructions can be being executed simultaneously within the execution unit. Further, a set of at least ‘n’ logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected.

Abstract: A floating point unit having a register bank containing a plurality of registers supports vector operations that execute a specified operation a plurality of times upon a sequence of data values form different registers. The register bank is divided into subsets and with the sequence of registers used in a vector operation wrapping within a subset. The subsets comprise disjoint, contiguous ranges of register numbers. The wrapping within ranges allows compact code and efficient to be provided for performing DSP operations, such as FIR filtering and matrix transformations.

Abstract: A floating point unit is described that performs addition operations. An adder 16 within the floating point unit receives a first input and a second input to generate a sum. This sum is subject to subsequent normalization by a normalizer 60 and rounding by an incrementer 64. If an operation is performed that is immediately followed by an addition operation using the result of the preceding operation, then the normalized but unrounded sum is fed back to the adder 16 together with an indication of its rounding requirement. This rounding requirement can be performed by the adder 16 in parallel with the execution of the following addition by using the carry-in bit of the adder 16 to apply any increment required to rounding of the preceding result.

Abstract: A floating point unit 10 provides a multiply-accumulate operation to determine a result B+(A*C). The multiplier 20 takes several processing cycles to determine the product (A*C). Whilst the multiplier 20 and its subsequent carry-save-adder 26 operate, an aligned value B' of the addend B is generated by an alignment-shifter 34. The aligned-addend B' may only partially overlap with the product (A*C) to which it is to be added using an adder 44. Any high-order-portion HOP of the aligned-addend B' that does not overlap with the product (A*C) must be subsequently concatenated with the output of the adder 44 that sums the product (A*C) with the overlapping portion of the aligned-addend B'. If the sum performed by the adder 44 generates a carry then it is an incremented version IHOP of the high-order-portion that should be concatenated with the output of the adder 44.

Abstract: A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8.ltoreq.Y-X.ltoreq.16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.

Abstract: Data processing apparatus in which successive data processing instructions are executed comprises: memory accessing means for accessing a data memory in response to one or more of the instructions, the memory accessing means comprising means for detecting whether each memory access is invalid; condition test means, responsive to a processing state of the apparatus generated by previously executed instructions and operable during execution of each instruction, for detecting whether that instruction should be executed; and conditional control means, responsive to the memory accessing means and to the condition test means, for preventing complete execution of a current instruction if either the memory accessing means detects that a memory access initiated by the preceding instruction is invalid or the condition test means detects that the current instruction should not be executed.

Abstract: A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 is responsive to program instruction words. At least one program instruction word includes a destination register bit field <dest> specifying a destination register of a result data word and a destination register write disable flag for disabling writing of that result data word to the destination register.

Abstract: A data processing system having a plurality of registers 10 and an arithmetic logic unit 20, 22, 24 includes program instruction words having a source register bit field Sn specifying one of the registers storing an input operand data word together with an input operand size flag indicating whether the input operand has an N-bit size or (N/2)-bit size together with a high/low location flag indicating which of the high order bit positions or low order bit positions stores the input operand if it is of the smaller size. It is preferred that the arithmetic logic unit is also able to perform parallel operation program instruction words operating independently upon (N/2)-bit input operand data words stored in respective halves of a register.

Abstract: A digital signal processing system is described in which a microprocessor unit 2 operating under control of microprocessor program instruction words controls data transfer to and from a data storage device 8 and the supply and fetching of data to and from a digital signal processing unit 4.

Abstract: A microprocessor is described having an arithmetic unit 8 that includes a dedicated hardware divider. The hardware divider is responsive to a plurality of different divide instruction codes to generate respective multi-bit portions of a quotient. Each divide instruction can be early terminated when the partial remainder is detected as being zero. Furthermore, subsequent divide instructions to calculate the remaining bits of the quotient can be skipped in response to a flag (Zflag) set within a current programming status register 28. In the described embodiment, a 32-bit divisor and 64-bit dividend serve to produce a 32-bit quotient and a 32-bit remainder. The generation of the 32-bit quotient takes place in response to four different divide instruction codes each responsible for generating a respective 8-bit portion of the quotient.

Abstract: A data processing system is described having a central processing unit (CPU) 4, a memory management unit (MMU) 6 and a cache memory 8. The CPU 4 makes cache writes in the same clock cycle that the data is output from the CPU 4. In a following clock cycle, the MMU 6 produces a signal IC indicating whether that storage operation was invalid. If the storage operation was invalid, then a flag associated with a cache storage line storing a plurality of output data words is set to indicate such invalid storage.