Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: A level-shift circuit translates a control signal to a level-shifted output. The level-shift circuit includes a pulse generator circuit for providing Set and Reset pulses based on the control signal and a level-shift circuit for translating the Set and Reset pulses to level-shifted Set and Reset pulses. First and second differential detectors are connected to monitor the level-shifted Set and Reset pulses to provide detection of communicated Set and Reset pulses despite the presence of transients in the level-shift circuit. A gate drive circuit employs the Set and Reset pulses communicated by the differential detectors to generate a gate drive signal.

Abstract: A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier.

Abstract: Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Abstract: Electronic circuitry and methods are disclosed for monitoring a portion of a write driver, for example, a steady state value of a write driver of a hard disk drive preamplifier. Based on a result of the monitoring, a condition, such as a fault, can be detected in the write driver. For example, apparatus for monitoring a write driver of a disk drive system comprises a comparator circuit coupled to an output of the write driver and configured to compare a value present at the output of the write driver with a reference value such that at least one condition associated with the write driver is detectable as a result of the comparison of the write driver output value and the reference value.

Abstract: An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.

Abstract: A voltage regulator, a method of regulating voltage and an IC including a voltage regulator. In one embodiment, the voltage regulator includes: (1) a DC precision amplifier configured to generate a DC precision signal based on a reference voltage and a regulated output of the voltage regulator and (2) a response amplifier, coupled in parallel with the DC precision amplifier, configured to generate an error signal based on the reference voltage and the regulated output, the response amplifier further configured to generate the regulated output based on a regulating signal comprised of the error signal and the DC precision signal. The DC precision amplifier may be a CMOS amplifier and the response amplifier may be a NPN amplifier.

Abstract: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device.

Abstract: A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

Abstract: A wafer containing integrated circuits having fuses which are selectively blown to trim circuit perimeters. The fuses are located adjacent scribe lanes, and fuse pads are located in the scribe lanes. The integrated circuits are trimmed by selectively energizing the fuse pads to blow selective fuses. When the integrated circuits are severed from the wafer, the fuse pads are severed from the integrated circuits.

Abstract: A method of testing a semiconductor circuit including a pair of contact pads, a biasing circuit for applying a voltage to the pair of contact pads, and a sensing circuit for providing a signal indicative of the voltage applied across the contact pads. The method includes determining a voltage gain and voltage offset of the sensing circuit while the biasing circuit is disabled. The method also includes enabling the biasing circuit to produce a voltage across the contact pads and determining, from the resulting output voltage produced by the sensing circuit, an actual output voltage produced by the biasing circuit at the contact pads based on the determined voltage gain and voltage offset of the sensing circuit.

Abstract: Herein is provided a display device for golfing-related items comprising a housing defining a periphery; a plurality of golf ball channels partially open to said periphery and receiving golf balls therein such that said golf balls are viewable through the portion of the golfball channels that opens to said periphery; and at least one item-retaining member selected from the group consisting of a score card slot retaining scorecards, a bore retaining ball markers, a pencil slot retaining score card pencils, a business card slot retaining business cards, and means retaining a divot repair tool.

Abstract: An error amplifier for use in a disk drive actuator system having an actuator motor for radially positioning a transducing head with respect to a rotatable disk is newly designed to enable full implementation as an integrated circuit. The error amplifier includes a switched-capacitor proportional-integral controller for comparing first and second differential input signals representing a respective actual current and commanded current for driving the actuator motor, and providing a differential output signal. A transconductor-capacitor filter is connected to filter the differential output signal of the switched-capacitor integrator, and provides a motor control signal to control the actuator motor.

Abstract: A pulse width modulation controller for a hard disc drive spindle motor controls the rapid spin up of the spindle motor from a stop condition to normal operating speed using a multi-level peak current limiting and six state commutation. At the beginning of each commutation state, peak motor current is limited to less than its steady state peak value for a selected number of pulses. The peak current target then returns its normal level for the remainder of the commutation state. By reducing the peak current target for several pulses after each commutation state change, the effective supply current spike at commutation is reduced or eliminated.

Abstract: A wafer containing integrated circuits having fuses which are selectively blown to trim circuit perimeters. The fuses are located adjacent scribe lanes, and fuse pads are located in the scribe lanes. The integrated circuits are trimmed by selectively energizing the fuse pads to blow selective fuses. When the integrated circuits are severed from the wafer, the fuse pads are severed from the integrated circuits.

Abstract: A motor controller for a three-phase spindle motor used in the hard disc drive provides pulse width modulated (PWM) signals used to drive the motor. The PWM signals have duty cycles which are a function of rotational position of the motor, a magnitude control signal, a stored set of main waveform coefficients, a stored set of modifier coefficients, and a modifier signal. By varying the modifier signal, the duty cycle of the PWM signals can be varied to adjust the shape of the motor current waveform to match the torque profile of the motor.

Abstract: A pulse width modulation controller for a hard disc drive spindle motor controls the rapid spin up of the spindle motor from a stop condition to normal operating speed using a multi-level peak current limiting and six state commutation. At the beginning of each commutation state, peak motor current is limited to less than its steady state peak value for a selected number of pulses. The peak current target then returns its normal level for the remainder of the commutation state. By reducing the peak current target for several pulses after each commutation state change, the effective supply current spike at commutation is reduced or eliminated.

Abstract: A motor controller for a three-phase spindle motor used in the hard disc drive provides pulse width modulated (PWM) signals used to drive the motor. The PWM signals have duty cycles which are a function of rotational position of the motor, a magnitude control signal, a stored set of main waveform coefficients, a stored set of modifier coefficients, and a modifier signal. By varying the modifier signal, the duty cycle of the PWM signals can be varied to adjust the shape of the motor current waveform to match the torque profile of the motor.