Patents by Inventor David Wei Wang

David Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110291268
    Abstract: A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 1, 2011
    Inventors: David Wei WANG, An-Hong Liu, Hsiang-Ming Huang, Yi-Chang Lee
  • Publication number: 20110180274
    Abstract: An apparatus and method for plugging a wellbore completion. The apparatus includes a body and a variable diameter ring. The body includes a first portion having a first diameter, and a second portion having a second diameter that is smaller than the first diameter. The variable diameter ring is disposed around the body and slidable on the first and second portions. The ring is configured to engage a flow path reduction device when located on the first portion, and to move past the flow path reduction device when located on the second portion.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Applicant: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: David Wei Wang, Gary L. Rytlewski
  • Patent number: 7981725
    Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: July 19, 2011
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20110168406
    Abstract: A completions system utilizing a unique hydraulic coupling. The system includes an upper completion stinger configured for coupling to a lower completion tubular. Both the stinger and the tubular are outfitted with hydraulic lines therethrough. Thus, as the stinger is coupled to the tubular, hydraulic lines are also coupled. However, the termination of each line is sealingly covered by a slidable sleeve in advance of attaining the coupling between the stinger and tubular. Therefore, the lines are protected from contamination during potentially significant periods of well deployment that may occur in advance of completed coupling and system installation. Furthermore, the manner of hydraulic coupling between the stinger and tubular reduces the likelihood of damage to the hydraulic lines during the installation process.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 14, 2011
    Applicant: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Michael Hui Du, Gary Rytlewski, David Wei Wang
  • Patent number: 7973310
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 5, 2011
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Patent number: 7960214
    Abstract: A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: June 14, 2011
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20110035580
    Abstract: A media access control (MAC) security (MACsec) function block may implement MACsec protocols on a network. A physical layer device (PHY) may connect to the MACsec function block and an interface register configured to store command information for the MACsec function block. A central processing unit (CPU) may provide the command information for the MACsec function block to the PHY via a management data input/output (MDIO) bus. The PHY may execute either a read command or a write command against the MACsec function block based on the command information, receive, from the MACsec function block, a response corresponding to the execution of the read command or write command against the MACsec function block, and provide the response to the CPU via the MDIO bus.
    Type: Application
    Filed: September 17, 2009
    Publication date: February 10, 2011
    Applicant: Broadcom Corporation
    Inventors: David (Wei) Wang, Daniel Tai
  • Patent number: 7866708
    Abstract: An apparatus includes a connector to connect a first tubing section and a second tubing section together. The connector that includes a body that includes a first opening to receive the first tubing section, a second opening to receive the second tubing section, and a passageway. The apparatus includes a member that is adapted to be moved from a retracted position to an extended position to form a sealed connection between a tubular member that is connected to the first tubing section and the passageway.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: January 11, 2011
    Assignee: Schlumberger Technology Corporation
    Inventors: Craig D. Johnson, Matthew R. Hackworth, Michael D. Langlais, David Wei Wang, Laurent Alteirac, Stephane J. Virally, Jason Bigelow, Kerby J. Dufrene, Bruno Khan, Martin Prado, Ashish Sharma
  • Patent number: 7847414
    Abstract: A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 7, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Patent number: 7798212
    Abstract: A technique is provided to facilitate connection of completion assemblies at a downhole location. A completion assembly comprises a control line conduit having a connector designed for coupling with a corresponding connector of a next adjacent completion assembly. A cover is selectively used to block entry of debris and other contaminants into the connector during deployment of the completion assembly downhole prior to engagement with the next adjacent completion of assembly.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: September 21, 2010
    Assignee: Schlumberger Technology Corporation
    Inventors: Victor M. Bolze, David Wei Wang, Rex C. Mennem, David L. Verzwyvelt
  • Patent number: 7749806
    Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 6, 2010
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20100151624
    Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Application
    Filed: March 1, 2010
    Publication date: June 17, 2010
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20100012313
    Abstract: According to one or more aspects of the present disclosure, a piezoelectric pump may include a hydraulic fluid path between a low pressure source and a high pressure tool port; a fluid disposed in the hydraulic fluid path; a piston in communication with the fluid; and a piezoelectric material connected to the piston to pump the fluid through the high pressure tool port.
    Type: Application
    Filed: July 17, 2009
    Publication date: January 21, 2010
    Applicant: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Colin Longfield, David Wei Wang, Gary L. Rytlewski
  • Publication number: 20100007001
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Patent number: 7638880
    Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 29, 2009
    Assignees: ChipMOS Technologies Inc., ChipMOS Technologies (Bermuda) Ltd.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20080308916
    Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 18, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20080308915
    Abstract: A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit substrate and the first chip is electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first bonding pads of the first chip. The component is disposed over the first active surface of the first chip. The first adhesive layer adhered between the first active surface and the component without covering the first bonding pads and includes a first B-staged adhesive layer adhered on a portion of the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 18, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20080308914
    Abstract: A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and the component and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate.
    Type: Application
    Filed: August 26, 2008
    Publication date: December 18, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20080268572
    Abstract: A fabricating process of chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate or on the second substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the first B-staged adhesive layer and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Application
    Filed: July 8, 2008
    Publication date: October 30, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang
  • Publication number: 20080268570
    Abstract: A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provide, wherein a plurality of bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first B-staged adhesive layer and the second B-staged adhesive layer such that each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
    Type: Application
    Filed: July 8, 2008
    Publication date: October 30, 2008
    Applicants: CHIPMOS TECHNOLOGIES INC., CHIPMOS TECHNOLOGIES (BERMUDA) LTD.
    Inventors: Geng-Shin Shen, David Wei Wang