Patents by Inventor Daxin Mao
Daxin Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10354956Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.Type: GrantFiled: January 5, 2018Date of Patent: July 16, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Daxin Mao, Hiroyuki Ogawa, Johann Alsmeier
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Publication number: 20190214344Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.Type: ApplicationFiled: January 5, 2018Publication date: July 11, 2019Inventors: Jixin Yu, Daxin Mao, Hiroyuki Ogawa, Johann Alsmeier
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Patent number: 10269620Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.Type: GrantFiled: September 23, 2016Date of Patent: April 23, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Sung Tae Lee, Yao-sheng Lee, Johann Alsmeier
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Patent number: 10256248Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.Type: GrantFiled: June 7, 2016Date of Patent: April 9, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani, Hiroyuki Ogawa, Chun Ge, Daxin Mao, Yanli Zhang, Alexander Chu, Yan Li
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Patent number: 10249640Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.Type: GrantFiled: June 8, 2016Date of Patent: April 2, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Zhenyu Lu, Alexander Chu, Kensuke Yamaguchi, Hiroyuki Ogawa, Daxin Mao, Yan LI, Johann Alsmeier
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Patent number: 10217746Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electricType: GrantFiled: January 11, 2018Date of Patent: February 26, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Tae-Kyung Kim, Raghuveer S. Makala, Yanli Zhang, Hiroyuki Kinoshita, Daxin Mao, Jixin Yu, Yiyang Gong, Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi
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Patent number: 10115732Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.Type: GrantFiled: February 22, 2016Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Zhenyu Lu, Daxin Mao, Yanli Zhang, Andrey Serov, Chun Ge, Johann Alsmeier
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Patent number: 10056399Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leasType: GrantFiled: February 28, 2017Date of Patent: August 21, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiying Costa, Daxin Mao, Christopher Petti, Dana Lee, Yao-Sheng Lee
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Publication number: 20180182771Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leasType: ApplicationFiled: February 28, 2017Publication date: June 28, 2018Inventors: Xiying Costa, Daxin Mao, Christopher Petti, Dana Lee, Yao-Sheng Lee
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Patent number: 10008570Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.Type: GrantFiled: March 14, 2017Date of Patent: June 26, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Jixin Yu, Kento Kitamura, Tong Zhang, Chun Ge, Yanli Zhang, Satoshi Shimizu, Yasuo Kasagi, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Johann Alsmeier, James Kai
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Patent number: 9985046Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.Type: GrantFiled: June 13, 2016Date of Patent: May 29, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Jixin Yu, Koji Miyata, Makoto Yoshida, Johann Alsmeier, Hiro Kinoshita, Daxin Mao
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Publication number: 20180122906Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.Type: ApplicationFiled: March 14, 2017Publication date: May 3, 2018Inventors: Jixin YU, Kento KITAMURA, Tong ZHANG, Chun GE, Yanli ZHANG, Satoshi SHIMIZU, Yasuo KASAGI, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Johann ALSMEIER, James KAI
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Patent number: 9859363Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.Type: GrantFiled: May 16, 2016Date of Patent: January 2, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Kota Funayama, Chun-Ming Wang, Jixin Yu, Chenche Huang, Tong Zhang, Daxin Mao, Johann Alsmeier, Makoto Yoshida, Lauren Matsumoto
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Patent number: 9853043Abstract: A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-stType: GrantFiled: August 25, 2015Date of Patent: December 26, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhenyu Lu, Daxin Mao, Tong Zhang, Johann Alsmeier, Wenguang Shi, Henry Chien
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Publication number: 20170358594Abstract: A linear mark extending perpendicular to a primary step direction of stepped terrace for a three-dimensional memory device can be employed as a reference feature for aligning a trimming material layer before initiating an etch-and-trim process sequence. The linear mark can be formed as a linear trench or a linear rail structure. The distance between a sidewall of each trimming material layer and the linear mark can be measured at multiple locations that are laterally spaced apart perpendicular to the primary step direction to provide statistically significant data points, which can be employed to provide an enhanced control of the staircase patterning process. Likewise, locations of patterned stepped surfaces can be measured at multiple locations to provide enhanced control of the locations of vertical steps in the stepped terrace.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Inventors: Zhenyu LU, Jixin YU, Koji MIYATA, Makoto YOSHIDA, Johann ALSMEIER, Hiro KINOSHITA, Daxin MAO
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Publication number: 20170358593Abstract: A semiconductor structure includes a memory-level assembly located over a substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack. Each of the at least one an alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers, and each of the electrically conductive layers in the at least one alternating stack includes a respective opening such that a periphery of a respective spacer dielectric portion located in the opening contacts a sidewall of the respective electrically conductive layers. At least one through-memory-level via structure vertically extends through each of the spacer dielectric portions and the insulating layers.Type: ApplicationFiled: June 8, 2016Publication date: December 14, 2017Inventors: Jixin YU, Zhenyu LU, Alexander CHU, Kensuke YAMAGUCHI, Hiroyuki OGAWA, Daxin MAO, Yan LI, Johann ALSMEIER
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Publication number: 20170352678Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Zhenyu LU, Jixin YU, Johann ALSMEIER, Fumiaki TOYAMA, Yuki MIZUTANI, Hiroyuki OGAWA, Chun GE, Daxin MAO, Yanli ZHANG, Alexander CHU, Yan LI
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Publication number: 20170243879Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.Type: ApplicationFiled: February 22, 2016Publication date: August 24, 2017Inventors: Jixin YU, Zhenyu LU, Daxin MAO, Yanli ZHANG, Andrey SEROV, Chun GE, Johann ALSMEIER
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Publication number: 20170236896Abstract: A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.Type: ApplicationFiled: May 16, 2016Publication date: August 17, 2017Inventors: Zhenyu LU, Kota FUNAYAMA, Chun-Ming WANG, Jixin YU, Chenche HUANG, Tong ZHANG, Daxin MAO, Johann ALSMEIER, Makoto YOSHIDA, Lauren MATSUMOTO
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Publication number: 20170236746Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.Type: ApplicationFiled: September 23, 2016Publication date: August 17, 2017Inventors: Jixin YU, Zhenyu LU, Hiroyuki OGAWA, Daxin MAO, Kensuke YAMAGUCHI, Sung Tae LEE, Yao-sheng LEE, Johann ALSMEIER