Patents by Inventor Dean A. Klein

Dean A. Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7898892
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7861094
    Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a non-volatile memory. The key may also be derived at least in part from user input to the computer.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: December 28, 2010
    Assignee: Round Rock Research, LLC
    Inventor: Dean A. Klein
  • Publication number: 20100306461
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Application
    Filed: July 2, 2010
    Publication date: December 2, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7840952
    Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: November 23, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7836374
    Abstract: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20100226141
    Abstract: A pliable combined support for decorative lighting comprises a receiver light mount having a light retaining notch and an insert light mount having a light retaining notch. The receiver light mounting bracket assembly is provided with an elongated channel with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The insert light mounting bracket has an elongated insert with a tangential extrusion with holes for mounting to a surface or structure and gripping points for receiving lights. The receiver and insert mounting brackets may be coupled for a rotational frictional attachment whereby the lighting may be displayed in a fixed position along a building, structure, or surface. The receiver and insert mounting brackets can also provide a storage method that will allow lights to be stacked or boxed without tangling.
    Type: Application
    Filed: March 7, 2009
    Publication date: September 9, 2010
    Inventors: Dean A. Klein, Rene Marie Smith
  • Patent number: 7778092
    Abstract: A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7732883
    Abstract: Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a device. The optical element is formed by applying a force to lateral portions of a liquid material layer formed below an elastomeric material layer such that the liquid material layer has a radius of curvature sufficient to direct light to a light sensitive portion of the device, after which the liquid material layer is exposed to conditions which maintain the radius of curvature after the lateral force is removed.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: June 8, 2010
    Assignee: Aptina Imaging Corp.
    Inventors: Dean A. Klein, Ian Blasch
  • Publication number: 20100115221
    Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.
    Type: Application
    Filed: January 11, 2010
    Publication date: May 6, 2010
    Inventor: Dean A. Klein
  • Publication number: 20100082881
    Abstract: Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventor: Dean Klein
  • Publication number: 20100082857
    Abstract: Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventor: Dean Klein
  • Publication number: 20100066940
    Abstract: A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing. The LCD housing conducts light from the light source to the LCD. A method for conducting light is also disclosed. The method includes generating light and conducting the generated light through a LCD housing.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean A. Klein
  • Publication number: 20100054070
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Application
    Filed: November 12, 2009
    Publication date: March 4, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7657723
    Abstract: A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the appropriate memory pages to expedite the retrieval of information from memory referenced by instructions in the execution pipeline. A suitable compiler parses the source code and collects references to branch addresses, calls to other routines, or data references, and creates reference tables listing the addresses for these references at the beginning of each routine. These tables are received by the memory management processor as the instructions of the routine are beginning to be loaded into the execution pipeline, so that the memory management processor can begin opening memory pages where the referenced information is stored. Opening the memory pages where the referenced information is located before the instructions reach the instruction processor helps lessen memory latency delays which can greatly impede processing performance.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: February 2, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Publication number: 20100020247
    Abstract: One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task of computing the difference between successive frames of video data independently from the central processing unit. This frees the often-overburdened central processing unit from performing this time-consuming compression operation and can thereby improve the handling of video data. Thus, one embodiment of the present invention can be characterized as a method thr compressing video data in a computer system. This method includes receiving a stream of data from a current video frame in the computer system. It also includes computing a difference frame from the current video frame and a previous video frame “on-the-fly” as the current video frame streams into the computer system. The method additionally includes storing the difference frame in a memory in the computer system.
    Type: Application
    Filed: September 29, 2009
    Publication date: January 28, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Dean A. Klein
  • Publication number: 20100011150
    Abstract: Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device.
    Type: Application
    Filed: July 10, 2008
    Publication date: January 14, 2010
    Inventor: Dean Klein
  • Patent number: 7630024
    Abstract: A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing. The LCD housing conducts light from the light source to the LCD. A method for conducting light is also disclosed. The method includes generating light and conducting the generated light through a LCD housing.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: December 8, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7623392
    Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: November 24, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 7615729
    Abstract: A method and apparatus for focusing an image on a pixel array. The method includes the steps of continuously changing the distance between a lens and a pixel array between a first distance and a second distance and obtaining an image projected onto the pixel array through the distance is changing. The apparatus includes a lens and an electromechanical structure to continuously change the distance between the lens and the pixel array between the first distance and the second distance.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: November 10, 2009
    Assignee: Aptina Imaging Corporation
    Inventor: Dean A. Klein
  • Publication number: 20090265504
    Abstract: Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 22, 2009
    Applicant: Micron Technology, Inc.
    Inventor: Dean A. Klein