Abstract: A clock plane is embedded in the housing of a semiconductor chip package where the plane is connected to two or more clock pads on the semiconductor die through vias, bonding fingers and bonding wires. The two or more clock pads are connected by one or more clock lines. The clock plane is connected by means of a via to a clock iput pin. In this manner, a clock signal fed to the clock input pin is driven through the one or more clock line with its tributaries from two separate locations by two or more input clock pads. This reduces clock skew and permits a smaller area of the die surface to be taken up by the clock lines.

Abstract: The leadframe of this invention includes a die attach pad and leads with lead tips in the vicinity of the pad. Alternate lead tips have been bent upwards into one plane and the remaining lead tips are bent downwards into a different plane. This design enables a denser packing of lead tips without fear of electrical shorts than the conventional design where the lead tips are in the same plane.