Patents by Inventor Dean Probst
Dean Probst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7998819Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.Type: GrantFiled: August 3, 2010Date of Patent: August 16, 2011Assignee: Fairchild Semiconductor CorporationInventors: Bruce D. Marchant, Dean Probst
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Publication number: 20110003449Abstract: A method of forming a semiconductor device includes the following. Removing portions of a silicon layer such that a trench having sidewalls which fan out near the top of the trench to extend directly over a portion of the silicon layer is formed in the silicon layer; and forming source regions in the silicon layer adjacent the trench sidewall such that the source regions extend into the portions of the silicon layer directly over which the trench sidewalls extend.Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Inventors: Robert Herrick, Becky Losee, Dean Probst
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Publication number: 20100317168Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.Type: ApplicationFiled: August 3, 2010Publication date: December 16, 2010Inventors: Bruce D. Marchant, Dean Probst
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Patent number: 7799636Abstract: A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall.Type: GrantFiled: September 25, 2009Date of Patent: September 21, 2010Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
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Patent number: 7781835Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.Type: GrantFiled: January 12, 2009Date of Patent: August 24, 2010Assignee: Fairchild Semiconductor CorporationInventors: Bruce D. Marchant, Dean Probst
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Publication number: 20100176452Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.Type: ApplicationFiled: January 12, 2009Publication date: July 15, 2010Inventors: Bruce D. Marchant, Dean Probst
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Publication number: 20100015769Abstract: A method of forming a semiconductor device includes the following. A masking layer with opening is formed over a silicon layer. The silicon layer is isotropically etched through the masking layer openings so as to remove bowl-shaped portions of the silicon layer, each of which includes a middle portion and outer portions extending directly underneath the masking layer. The outer portions form outer sections of corresponding trenches. Additional portions of the silicon layer are removed through the masking layer openings so as to form a middle section of the trenches which extends deeper into the silicon layer than the outer sections of the trenches. A first doped region of a first conductivity type is formed in an upper portion of the silicon layer. An insulating layer is formed within each trench, and extends directly over a portion of the first doped region adjacent each trench sidewall.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Inventors: Robert Herrick, Becky Losee, Dean Probst
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Patent number: 7598144Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: GrantFiled: December 7, 2007Date of Patent: October 6, 2009Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Dean Probst, Fred Session
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Patent number: 7595524Abstract: A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.Type: GrantFiled: March 17, 2008Date of Patent: September 29, 2009Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
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Publication number: 20090111227Abstract: A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region.Type: ApplicationFiled: December 30, 2008Publication date: April 30, 2009Inventors: Christopher Boguslaw Kocon, Steven Sapp, Paul Thorup, Dean Probst, Robert Herrick, Becky Losee, Hamza Yilmaz, Christopher Lawrence Rexer, Daniel Calafut
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Publication number: 20080164519Abstract: In accordance with an embodiment of the present invention, a FET is formed as follows. An exposed surface area of a silicon layer where silicon can be removed is defined. A portion of the silicon layer is removed to form a middle section of a trench extending into the silicon layer from the exposed surface area of the silicon layer. Additional exposed surface areas of the silicon layer where silicon can be removed are defined. Additional portions of the silicon layer are removed to form outer sections of the trench such that the outer sections of the trench extend into the silicon layer from the additional exposed surface areas of the silicon layer. The middle section of the trench extends deeper into the silicon layer than the outer sections of the trench.Type: ApplicationFiled: March 17, 2008Publication date: July 10, 2008Inventors: Robert Herrick, Becky Losee, Dean Probst
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Patent number: 7385248Abstract: A field effect transistor (FET) includes a trench extending into a silicon region of a first conductive type. A shield insulated from the silicon region by a shield dielectric extends in a lower portion of the trench. A gate electrode is in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD). The IPD comprises a conformal layer of dielectric and a thermal oxide layer.Type: GrantFiled: August 9, 2005Date of Patent: June 10, 2008Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Dean Probst, Fred Session
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Publication number: 20080090339Abstract: A method of forming shielded gate trench FET includes the following steps. A trench is formed in a silicon region of a first conductivity type. A shield electrode is formed in a bottom portion of the trench. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: ApplicationFiled: December 7, 2007Publication date: April 17, 2008Inventors: Robert Herrick, Dean Probst, Fred Session
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Patent number: 7344943Abstract: A semiconductor device is formed as follows. A plurality of trenches is formed in a silicon layer. An insulating layer filling an upper portion of each trench is formed. Exposed silicon is removed from adjacent the trenches to expose an edge of the insulating layer in each trench, such that the exposed edge of the insulating layer in each trench defines a portion of each contact opening formed between every two adjacent trenches.Type: GrantFiled: April 20, 2005Date of Patent: March 18, 2008Assignee: Fairchild Semiconductor CorporationInventors: Robert Herrick, Becky Losee, Dean Probst
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Publication number: 20070082441Abstract: A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.Type: ApplicationFiled: October 23, 2006Publication date: April 12, 2007Inventors: Nathan Kraft, Ashok Challa, Steven Sapp, Hamza Yilmaz, Daniel Calafut, Dean Probst, Rodney Ridley, Thomas Grebs, Christopher Kocon, Joseph Yedinak, Gary Dolny
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Publication number: 20070042551Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.Type: ApplicationFiled: August 10, 2006Publication date: February 22, 2007Inventors: Brian Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Probst
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Publication number: 20070037327Abstract: A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.Type: ApplicationFiled: August 9, 2005Publication date: February 15, 2007Inventors: Robert Herrick, Dean Probst, Fred Session
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Publication number: 20060273386Abstract: A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.Type: ApplicationFiled: May 24, 2006Publication date: December 7, 2006Inventors: Hamza Yilmaz, Daniel Calafut, Christopher Kocon, Steven Sapp, Dean Probst, Nathan Kraft, Thomas Grebs, Rodney Ridley, Gary Dolny, Bruce Marchant, Joseph Yedinak
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Publication number: 20060214222Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: ApplicationFiled: May 31, 2006Publication date: September 28, 2006Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J. Lee, Peter Wilson, Joseph Yedinak, J. Jung, H. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey
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Publication number: 20060214221Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.Type: ApplicationFiled: May 31, 2006Publication date: September 28, 2006Inventors: Ashok Challa, Alan Elbanhawy, Thomas Grebs, Nathan Kraft, Dean Probst, Rodney Ridley, Steven Sapp, Qi Wang, Chongman Yun, J.G. Lee, Peter Wilson, Joseph Yedinak, J.Y. Jung, H.C. Jang, Babak Sani, Richard Stokes, Gary Dolny, John Mytych, Becky Losee, Adam Selsley, Robert Herrick, James Murphy, Gordon Madson, Bruce Marchant, Christopher Rexer, Christopher Kocon, Debra Woolsey