Patents by Inventor Debendra Mallik

Debendra Mallik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140251669
    Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.
    Type: Application
    Filed: April 24, 2012
    Publication date: September 11, 2014
    Inventors: Mathew J. Manusharow, Mihir K. Roy, Kaladhar Radhakrishnan, Debendra Mallik, Edward A. Burton
  • Publication number: 20140217585
    Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
    Type: Application
    Filed: December 22, 2011
    Publication date: August 7, 2014
    Inventors: Debendra Mallik, Robert L. Sankman
  • Publication number: 20140205851
    Abstract: An interconnect structure for electrically joining two surfaces includes magnetic attachment structures and an anisotropic conductive adhesive (ACA). Magnetic attachment structures on a first surface are magnetically attracted to magnetic attachment structures on a second surface. Opposing magnetic attachment structures are joined via an ACA, which conducts electricity when compressed, and is electrically insulating when not compressed. The magnetic attraction between opposing magnetic attachment structures generates a sufficient force to maintain compression of the intervening ACA in order to sustain a desired level of electrical conductivity between the first surface and second surface. A method for joining two surfaces using the interconnect structure is disclosed. Additionally, a magnetic anisotropic conductive adhesive having magnetic conductive particles dispersed therein is disclosed.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Inventors: Ravindranath V. MAHAJAN, Aleksandar ALEKSOV, Debendra MALLIK, Ian A. YOUNG, Rajasekaran SWAMINATHAN, Sairam AGRAHARAM, John S. GUZEK
  • Publication number: 20140191419
    Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 10, 2014
    Applicant: INTEL CORPORATION
    Inventors: Debendra Mallik, Ram S. Viswanath, Sriram Srinivasan, Mark T. Bohr, Andrew W. Yeoh, Sairam Agraharam
  • Publication number: 20140176367
    Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Sasikanth Manipatruni, Kelin J. Kuhn, Debendra Mallik, John C. Johnson
  • Publication number: 20140173716
    Abstract: Managing and accessing personal data is described. In one example, an apparatus has an application processor, a memory to store data, a receive and a transmit array coupled to the application processor to receive data to store in the memory and to transmit data stored in the memory through a wireless interface, and an inertial sensor to receive user commands to authorize the processor to receive and transmit data through the receive and transmit array.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Inventors: Sasikanth Manipatruni, Kelin J. Kuhn, Debendra Mallik, John C. Johnson
  • Publication number: 20140165269
    Abstract: A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Inventors: ALEKSANDAR ALEKSOV, RAVINDRANATH V. MAHAJAN, SAIRAM AGRAHARAM, IAN A. YOUNG, JOHN C. JOHNSON, DEBENDRA MALLIK, JOHN S. GUZEK
  • Publication number: 20140098506
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 10, 2014
    Inventors: Debendra Mallik, Mihir Roy
  • Publication number: 20140091474
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Publication number: 20140029639
    Abstract: A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.
    Type: Application
    Filed: December 28, 2011
    Publication date: January 30, 2014
    Inventors: Edward A. Zarbock, Debendra Mallik
  • Patent number: 8617990
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 31, 2013
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Mihir K. Roy
  • Publication number: 20130270691
    Abstract: A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.
    Type: Application
    Filed: December 16, 2011
    Publication date: October 17, 2013
    Inventors: Debendra Mallik, Sridhar Narasimhan, Mathew J. Manusharow, Thomas A. Boyd
  • Publication number: 20130005162
    Abstract: Electronic assemblies and their manufacture are described. One assembly includes a land grid array package including a plurality of land contacts. The assembly also includes a first socket adapted to engage a first group of the plurality of land contacts, and a second socket adapted to engage a second group of the plurality of land contacts. The first socket and the second socket are each coupled to a board. The first socket and the second socket are separate structures on the board. Other embodiments are described and claimed.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventors: Debendra MALLIK, Ajit V. SATHE
  • Publication number: 20120153495
    Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Debendra Mallik, Mihir K. Roy
  • Patent number: 7932596
    Abstract: A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One or more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 26, 2011
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Robert L. Sankman
  • Patent number: 7867818
    Abstract: Methods and apparatuses to provide a stacked-die device comprised of stacked sub-packages. For one embodiment of the invention, each sub-package has interconnections formed on the die-side of the substrate for interconnecting to another sub-package. The dies and associated wires are protected by an encapsulant leaving an upper portion of each interconnection exposed. For one embodiment of the invention the encapsulant is a stencil-printable encapsulant and the upper portion of the interconnection is exposed by use of a patterned stencil during application of the encapsulant.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: January 11, 2011
    Inventors: Daewoong Suh, Debendra Mallik
  • Patent number: 7794236
    Abstract: An LGA socket for receiving substrate packages of various sizes and a method of fabricating the socket. In an embodiment, the socket has a planar surface for seating a substrate package. Socket contacts are disposed on the planar surface in a layout common to the layout of interconnects formed on the bottom of substrate packages the socket is designed to receive. A plurality of socket locating features is formed on the socket body to prevent lateral displacement of a reference substrate package. A corresponding number of package locating features are formed on the substrate body of packages larger than the reference substrate package. Each of the socket locating features meshes with the corresponding package locating feature of the larger package.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Brent Stone
  • Publication number: 20100151706
    Abstract: An LGA socket for receiving substrate packages of various sizes and a method of fabricating the socket. In an embodiment, the socket has a planar surface for seating a substrate package. Socket contacts are disposed on the planar surface in a layout common to the layout of interconnects formed on the bottom of substrate packages the socket is designed to receive. A plurality of socket locating features is formed on the socket body to prevent lateral displacement of a reference substrate package. A corresponding number of package locating features are formed on the substrate body of packages larger than the reference substrate package. Each of the socket locating features meshes with the corresponding package locating feature of the larger package.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Inventors: Debendra Mallik, Brent Stone
  • Patent number: 7656035
    Abstract: In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Sairam Agraharam, Carlton Hanna, Dongming He, Vasudeva Atluri, Debendra Mallik, Matthew Escobido, Sujit Sharan
  • Publication number: 20090314519
    Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Javier Soto, Charan Gurumurthy, Robert Nickerson, Debendra Mallik