Patents by Inventor Dejan S. Milojicic

Dejan S. Milojicic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11086660
    Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 10, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Merritt, Gerd Zellweger, Dejan S Milojicic
  • Publication number: 20210240945
    Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 5, 2021
    Applicant: Hewlett Packard Enterprise Development LP
    Inventors: John Paul STRACHAN, Dejan S. MILOJICIC, Martin FOLTIN, Sai Rahul CHALAMALASETTI, Amit S. SHARMA
  • Patent number: 11075801
    Abstract: Systems and methods for system reconfiguration of a computing system that includes a plurality of memory and computing resources, may include: assigning a reconfiguration capability to a user, the reconfiguration capability granting the user a right to reconfigure at least one of memory and computing resources in the computing system; a controller of the computing system receiving a reconfiguration request from a user for a requested system reconfiguration along with that user's configuration capability; the controller of the computing system verifying that the user from which the reconfiguration request was received has the rights to make the requested system reconfiguration; and the controller of the system executing the requested system reconfiguration if the user has the rights to make the requested system reconfiguration.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: July 27, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Dejan S. Milojicic
  • Publication number: 20210201136
    Abstract: A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
    Type: Application
    Filed: April 30, 2018
    Publication date: July 1, 2021
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, John Paul Strachan, Sergey Serebryakov
  • Publication number: 20210133624
    Abstract: In exemplary aspects, a golden data structure can be used to validate the stability of machine learning (ML) models and weights. The golden data structure includes golden input data and corresponding golden output data. The golden output data represents the known correct results that should be output by a ML model when it is run with the golden input data as inputs. The golden data structure can be stored in a secure memory and retrieved for validation separately or together with the deployment of the ML model for a requested ML operation. If the golden data structure is used to validate the model and/or weights concurrently with the performance of the requested operation, the golden input data is combined with the input data for the requested operation and run through the model. Relevant outputs are compared with the golden output data to validate the stability of the model and weights.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Sai Rahul Chalamalasetti, Sergey Serebryakov, Dejan S. Milojicic
  • Patent number: 10983831
    Abstract: Examples relate to firmware-based provisioning of hardware resources. In some of the examples, firmware discovers and takes ownership of a hardware resource. At this stage, the firmware performs a test to verify the hardware resource. The firmware then assigns the hardware resource to an OS instance. At this stage, the firmware can suspend assigning further hardware resources to the OS instance in response to a satisfied notification from the OS instance.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 20, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dejan S. Milojicic, Derek Schumacher, Zhikui Wang
  • Publication number: 20210049125
    Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
    Type: Application
    Filed: October 16, 2020
    Publication date: February 18, 2021
    Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
  • Patent number: 10884953
    Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 5, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dejan S Milojicic, Chris I Dalton, Paolo Faraboschi, Kirk M Bresniker
  • Patent number: 10848380
    Abstract: Examples disclosed herein relate to computer system managements. Some of the examples disclosed herein enable identifying properties of a computer system and adjusting a degree of manageability of the computer system based on the properties of the computer system.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Carey Huscroft, Dejan S. Milojicic, Stephen B. Lyle
  • Patent number: 10846016
    Abstract: In one example in accordance with the present disclosure, enforcement of memory reference object loading indirection is described. According to a method, at a register, it is determined from an indirection counter of a first memory referencing object (MRO) in one of a number of registers of a processor of the computing device, whether a second MRO is loadable. When the indirection counter of the first MRO indicates a second MRO is loadable, the second MRO is loaded from the memory device to one of the number of registers. The second MRO also includes an indirection counter. The indirection counter of the loaded second MRO is changed, at the register that contains it, based on the indirection counter of the first MRO to enforce a degree of MRO loading indirection. Further, MRO loading is prohibited when an indirection counter reaches zero by invalidating a capability counter of a subsequent MRO at the register.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dejan S. Milojicic, Leonid Azriel, Lukas Humbel
  • Patent number: 10838909
    Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
  • Patent number: 10795782
    Abstract: Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: October 6, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Dejan S. Milojicic, Keith Packard, Michael Woodacre, Andrew R. Wheeler
  • Patent number: 10754792
    Abstract: Example implementations relate to persistent virtual address spaces. In one example, persistent virtual address spaces can employ a non-transitory processor readable medium including instructions to receive a whole data structure of a virtual address space (VAS) associated with a process, where the whole data structure includes data and metadata of the VAS, and store the data and the metadata of the VAS in a non-volatile memory to form a persistent VAS (PVAS).
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Merritt, Gerd Zellweger, Dejan S. Milojicic
  • Patent number: 10698737
    Abstract: A Neural Network (NN) scheduler and techniques to implement features of different possible NN schedulers are disclosed. In a first example, an NN scheduler that accepts NN models in an interoperable format and performs optimizations on this interoperable format as part of converting it to a run-time format is provided. In a second example, an NN scheduler analyzes operations and annotations associated with those operations to determine scheduling options based on hardware availability, data availability, hardware efficiency, processor affinity, etc. In a third example, an NN scheduler that may be integrated with a feed-back loop to recognize actual run-time attributes may be used to “learn” and adapt to change its future scheduling behavior. Each of these examples may be integrated individually, or together, to provide an NN scheduler that optimizes and adapts processing functions for an NN model either prior to processing or for just-in-time determination of operation scheduling.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Guilherme James De Angelis Fachini, Dejan S. Milojicic, Gustavo Henrique Rodrigues Pinto Tomas, Francisco Plinio Oliveira Silveira
  • Patent number: 10644981
    Abstract: Example implementations relate to scaling a processing system. An example implementation includes receiving an application having a number of operators for performing a service in the processing system. A metric of the processing system may be monitored while the application runs, and the processing system may be scaled where the metric surpasses a threshold. In an example, the processing system may be scaled by increasing or decreasing the number of operators of the application.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 5, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Yuan Chen, Dejan S. Milojicic, Jack Yanxin Li
  • Patent number: 10628057
    Abstract: An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 21, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Alexander Leslie Richardson, Moritz Josef Hoffmann, Dejan S. Milojicic
  • Patent number: 10628328
    Abstract: Methods and systems directed to a memory-side memory controller for interpreting capabilities and returning datasets to a Central Processing Unit (CPU) are provided. The CPU is configured to translate a first virtual address from a first capability to a first physical address, wherein the first capability is sent by a client application. The CPU is further configured to send the first physical address to the memory-side memory controller through a memory fabric. The memory-side memory controller loads a second capability located in the first physical address from an external memory through the memory fabric, interprets an address encoded within the second capability as a second physical address, and returns a dataset located in the second physical address from the external memory to the CPU through the memory fabric.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 21, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Moritz J. Hoffmann, Alexander Richardson, Dejan S. Milojicic
  • Publication number: 20200097440
    Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
  • Patent number: 10592437
    Abstract: Memory blocks are associated with each memory level of a hierarchy of memory levels. Each memory block has a matching key capability (MaKC). The MaKC of a memory block governs access to the memory block, in accordance with permissions specified by the MaKC. The MaKC of a memory block can uniquely identify the memory block across the hierarchy of memory levels, and can be globally unique across the memory blocks. An MaKC of a memory block includes a block protection key (BPK) stored with the memory block, and an execution protection key (EPK). If a provided EPK for a memory block matches the memory block's BPK upon comparison, access to the memory block is allowed according to the permissions specified by the MaKC.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geoffrey Ndu, Dejan S. Milojicic, Paolo Faraboschi, Chris I. Dalton
  • Patent number: 10592431
    Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Marshall Merritt, Gerd Zellweger, Dejan S. Milojicic, Paolo Faraboschi