Patents by Inventor Dengtao Zhao
Dengtao Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825513Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.Type: GrantFiled: June 26, 2018Date of Patent: November 3, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Deepanshu Dutta, Zhenming Zhou
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Publication number: 20200258558Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.Type: ApplicationFiled: May 17, 2019Publication date: August 13, 2020Applicant: Western Digital Technologies, Inc.Inventors: Abhijith Prakash, Anubhav Khandelwal, Deepanshu Dutta, Huai-Yuan Tseng, Wei Zhao, Dengtao Zhao
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Patent number: 10734070Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.Type: GrantFiled: June 26, 2018Date of Patent: August 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
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Patent number: 10726891Abstract: An apparatus includes a plurality of NAND strings in a block with word lines connected to cells of the NAND strings and select lines connected to select gate transistors of the NAND strings. A control circuit is configured to, after a read operation of memory cells of the block apply substantially zero volts to the global word lines to discharge the word lines to substantially zero volts. The control circuit is further configured to turn off the select gate transistors to isolate channels, turn off the block select transistors to isolate the word lines from the global word lines, and with the block select transistors turned off, apply a low positive voltage on the global word lines.Type: GrantFiled: May 17, 2019Date of Patent: July 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Abhijith Prakash, Anubhav Khandelwal, Deepanshu Dutta, Huai-Yuan Tseng, Wei Zhao, Dengtao Zhao
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Publication number: 20200234778Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: ApplicationFiled: April 3, 2020Publication date: July 23, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Patent number: 10643718Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: May 5, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Patent number: 10580504Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: March 3, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Patent number: 10553298Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.Type: GrantFiled: July 27, 2018Date of Patent: February 4, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Deepanshu Dutta
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Publication number: 20200035312Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.Type: ApplicationFiled: July 27, 2018Publication date: January 30, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Deepanshu Dutta
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Patent number: 10541037Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: GrantFiled: June 7, 2018Date of Patent: January 21, 2020Assignee: SanDisk Technologies LLCInventors: Dengtao Zhao, Deepanshu Dutta
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Publication number: 20190392893Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.Type: ApplicationFiled: June 26, 2018Publication date: December 26, 2019Inventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
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Publication number: 20190392894Abstract: A memory system includes a sense system configured to control parasitic noise sources by increasing selected bit line or channel voltages during sense stages. The increase may be tied to a triggering threshold voltage level. That is, while performing a memory operation, the sense system may increase the selected bit line voltage level dependent on a reference voltage level or memory state associated with a sense stage being above the triggering threshold level.Type: ApplicationFiled: June 26, 2018Publication date: December 26, 2019Applicant: SanDisk Technologies LLCInventors: Dengtao Zhao, Deepanshu Dutta, Zhenming Zhou
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Publication number: 20190378580Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Publication number: 20190378581Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Peng Zhang, Nan Lu, Deepanshu Dutta
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Publication number: 20190378579Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Applicant: SANDISK TECHNOLOGIES LLCInventors: Dengtao Zhao, Deepanshu Dutta
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Patent number: 10381083Abstract: A memory device and associated techniques avoid a disturb of a select gate transistor during an erase operation for memory cells in a string. During the erase operation, a channel potential gradient near the select gate transistors is reduced when the voltages of the bit line and the substrate are suitably controlled. In one approach, the voltage of the substrate at a source end of the memory string is increased to an intermediate level first before being increased to the erase voltage threshold level while the voltage of the bit line is held at a reference voltage level to delay floating the voltage of the bit line. Another approach builds off the first approach by temporarily decreasing the voltage of the bit line to a negative level before letting the voltage of the bit line to float at the same time as the voltage of the substrate is increased to the erase voltage threshold level.Type: GrantFiled: June 25, 2018Date of Patent: August 13, 2019Assignee: SanDisk Technologies LLCInventors: Xiang Yang, Kun-Huan Shih, Matthias Baenninger, Huai-Yuan Tseng, Dengtao Zhao, Deepanshu Dutta
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Patent number: 10109352Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: GrantFiled: April 10, 2017Date of Patent: October 23, 2018Assignee: Western Digital Technologies, Inc.Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Patent number: 9952939Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).Type: GrantFiled: April 30, 2015Date of Patent: April 24, 2018Assignee: Western Digital Technologies, Inc.Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
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Publication number: 20170352423Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: ApplicationFiled: April 10, 2017Publication date: December 7, 2017Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Patent number: 9672934Abstract: Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.Type: GrantFiled: February 25, 2016Date of Patent: June 6, 2017Assignee: Western Digital Technologies, Inc.Inventors: Guirong Liang, Haibo Li, Dengtao Zhao, Yongke Sun, Kroum S. Stoev