Abstract: A segmentation and reassembly processor (10) is disclosed for use in interfacing a group of time-division multiplexed lines (25) to a cell-based communication environment (20). The SAR uses a bit-table calendar (100) to schedule cells to be sent to the cell-based network. A cell service decision circuit (50) reads frame events from a frame advanced FIFO (40) and signals a cell builder (60) to assemble cells of data from a frame buffer (70) for transmission to a cell based output (50).

Abstract: A Micro Channel integrated circuit design capable of controlling high speed data and control transfers between a Micro Channel bus, a local processor, and a dedicated local data bus. The interface controller utilizes enhanced features of the Micro Channel and data buffering to achieve high speed data communications with various bit size Micro Channel devices. Queued commands are handled by flexibly programming the interface control operations. Interface control hardware increases the processing speed of data transfers by implementing performance critical functions of queuing in hardware. Extensive error checking and reporting and self-test give the interface controller advance functions as an input/output processor.