Abstract: The clock circuit is formed by an oscillator (10-12) which is coupled to a counter/divider circuit (15) provided with read accesses (30). In order to prevent falsification of its data, the circuit is formed as a protected casing and includes a protected access circuit (50) which is connected between said accesses and the counter/divider circuit. Furthermore, a circuit for monitoring the frequency of the oscillator may be provided (100-50).

Abstract: A data processing system, comprising a central unit, peripheral units, and input/output processors which are connected parallel to a common bus. The said processors centralize the exchanges between a plurality of peripheral units and the store. The data exchanges can be effected in the mode "programmed bus", in which the central unit is the master of the system, or by way of the "multiplex bus", where the exchange is controlled by the input/output processor in word blocks. The interruption system utilizes a second bus which is independent of the first bus, so that the simultaneous transfer of the interruption vectors and data is possible.