Patents by Inventor Denis Roland Beaudoin

Denis Roland Beaudoin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200127984
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20200110132
    Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: Denis Roland BEAUDOIN, Samuel Paul VISALLI
  • Patent number: 10567358
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20180367516
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 20, 2018
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 10110573
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 23, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20180034790
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20170104732
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: December 21, 2016
    Publication date: April 13, 2017
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9503265
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 22, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20160323253
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20160173283
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 16, 2016
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9305184
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9141831
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20150249654
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9098438
    Abstract: A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 4, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jose Luis Flores, Lewis Nardini, Ritesh Sojitra, Denis Roland Beaudoin
  • Patent number: 8983012
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Publication number: 20120121051
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Application
    Filed: January 25, 2012
    Publication date: May 17, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Patent number: 8171186
    Abstract: A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: May 1, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Brian Jason Karguth, Denis Roland Beaudoin, Akila Subramaniam
  • Publication number: 20120084575
    Abstract: A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
    Type: Application
    Filed: August 25, 2011
    Publication date: April 5, 2012
    Inventors: Jose Luis Flores, Lewis Nardini, Ritesh Sojitra, Denis Roland Beaudoin
  • Patent number: 8130889
    Abstract: A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Gregory Lee Christison
  • Publication number: 20120011351
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 12, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin