Patents by Inventor Denis Roland Beaudoin
Denis Roland Beaudoin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126560Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Inventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A.T. Jones, Jayant Thakur
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Patent number: 11853772Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: GrantFiled: August 16, 2022Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A. T. Jones, Jayant Thakur
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Publication number: 20230400512Abstract: A synchronization circuit includes a first synchronizer having a first data input, a first clock input, and first output; a second synchronizer having a second data input, a second clock input, and a second output; selection circuitry having first, second, third and fourth inputs, and a synchronized data output, the first and second inputs coupled to the first and second outputs, respectively; and storage circuitry having a storage data input coupled to the synchronized data output, a third clock input, and a feedback output coupled to the fourth input.Type: ApplicationFiled: August 29, 2023Publication date: December 14, 2023Inventors: Denis Roland BEAUDOIN, Samuel Paul VISALLI
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Publication number: 20230393975Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: ApplicationFiled: August 14, 2023Publication date: December 7, 2023Inventors: Denis Roland BEAUDOIN, Ritesh Dhirajlal SOJITRA, Samuel Paul VISALLI
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Patent number: 11796592Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: GrantFiled: January 12, 2022Date of Patent: October 24, 2023Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Samuel Paul Visalli
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Patent number: 11726907Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: GrantFiled: September 14, 2021Date of Patent: August 15, 2023Assignee: Texas Instruments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Samuel Paul Visalli
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Publication number: 20230169689Abstract: Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Gang HUA, Mihir Narendra MODY, Niraj NANDAN, Shashank DABRAL, Rajasekhar Reddy ALLU, Denis Roland BEAUDOIN
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Publication number: 20230171512Abstract: A technique for image processing, comprising: receiving input image data, wherein the image data is companded into a first bit depth, wherein the image data includes incomplete color values for pixels of the image data, and wherein the image data is associated with a first color space, interpolating the image data to generate color values for the incomplete color values for pixels of the image data, expanding the image data from the first bit depth to a second bit depth, wherein the color values of the expanded image data have a linear dynamic range, and wherein the second bit depth is higher than the first bit depth, converting the color values for pixels of the expanded image data from the first color space to a second color space, and compressing the color values for pixels of the image data to a third bit depth, the third bit depth lower than the second bit depth, and wherein the compressed color values have a nonlinear dynamic range.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Gang HUA, Mihir Narendra MODY, Niraj NANDAN, Shashank DABRAL, Rajasekhar Reddy ALLU, Denis Roland BEAUDOIN
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Publication number: 20220391219Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: August 16, 2022Publication date: December 8, 2022Inventors: Sriramakrishnan GOVINDARAJAN, Denis Roland BEAUDOIN, Gregory Raymond SHURTZ, Santhanakrishnan Badri NARAYANAN, Mark Adrian BRYANS, Mihir Narendra MODY, Jason A.T. JONES, Jayant THAKUR
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Patent number: 11436024Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: GrantFiled: December 2, 2019Date of Patent: September 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sriramakrishnan Govindarajan, Denis Roland Beaudoin, Gregory Raymond Shurtz, Santhanakrishnan Badri Narayanan, Mark Adrian Bryans, Mihir Narendra Mody, Jason A. T. Jones, Jayant Thakur
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Publication number: 20220137127Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Inventors: Denis Roland BEAUDOIN, Samuel Paul VISALLI
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Patent number: 11255905Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: GrantFiled: October 5, 2018Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Denis Roland Beaudoin, Samuel Paul Visalli
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Publication number: 20210406171Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: ApplicationFiled: September 14, 2021Publication date: December 30, 2021Inventors: Denis Roland BEAUDOIN, Ritesh Dhirajlal SOJITRA, Samuel Paul VISALLI
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Patent number: 11119909Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: GrantFiled: October 2, 2019Date of Patent: September 14, 2021Assignee: Texas Instmments IncorporatedInventors: Denis Roland Beaudoin, Ritesh Dhirajlal Sojitra, Samuel Paul Visalli
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Patent number: 10999263Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.Type: GrantFiled: December 19, 2019Date of Patent: May 4, 2021Assignee: Texas Instruments IncorporatedInventors: Amritpal Singh Mundra, Denis Roland Beaudoin
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Publication number: 20200210205Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.Type: ApplicationFiled: December 2, 2019Publication date: July 2, 2020Inventors: Sriramakrishnan GOVINDARAJAN, Denis Roland BEAUDOIN, Gregory Raymond SHURTZ, Santhanakrishnan Badri NARAYANAN, Mark Adrian BRYANS, Mihir Narendra MODY, Jason A.T. JONES, Jayant THAKUR
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Publication number: 20200183826Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.Type: ApplicationFiled: October 2, 2019Publication date: June 11, 2020Inventors: Denis Roland BEAUDOIN, Ritesh Dhirajlal SOJITRA, Samuel Paul VISALLI
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Publication number: 20200127984Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
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Publication number: 20200110132Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.Type: ApplicationFiled: October 5, 2018Publication date: April 9, 2020Inventors: Denis Roland BEAUDOIN, Samuel Paul VISALLI
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Packet accelerator ingress communication processor peripheral streaming interface, scheduler, buffer
Patent number: 10567358Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.Type: GrantFiled: August 24, 2018Date of Patent: February 18, 2020Assignee: Texas Instruments IncorporatedInventors: Amritpal Singh Mundra, Denis Roland Beaudoin