Abstract: Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode.

Abstract: This invention contemplates the provision of a noise immune integrated circuit receiver in which the voltage reference to one side of an emitter-coupled current switch moves in response to the input signal, in a direction opposite the input signal. This provides the gate with a threshold hysteresis, making it immune to noise without requiring a large swing in input signal.

Abstract: A high performance bipolar, field effect transistor (BiFET) logic circuit has minimal power supply requirements, allowing the circuit to be manufactured in higher density devices than current switched emitter follower (CSEF). BiFET logic circuit has a plurality of input lines and first and second output lines. A plurality of FET devices are connected in parallel each having a gate connected to a corresponding one of the input lines. Two bipolar transistors are connected as a differential pair, the parallel connection of said FET devices providing an input to the base of the first bipolar transistor while the base of the second bipolar transistor is supplied with a reference voltage. Output bipolar transistors connected as emitter followers drive the first and second output lines respectively.

Abstract: NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.

Abstract: A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits.

Abstract: Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.

Abstract: Logic circuit means for providing a binary output which is a predetermined logical function of a plurality of binary inputs, said logic circuit means including: at least first, second and third push-pull Darlington current sink (PPDCS) logic circuits, each said PPDCS logic circuit comprising: first, second and third transistors, each of said first, second and third transistors having an emitter, base and collector, said collector of said third transistor connected to a first source of potential and said emitter of said second transistor connected to a third source of potential; input circuit means, said input circuit means being adapted to receive n binary inputs, where n is a positive integer having a magnitude of two or greater, said input circuit means being connected to said collector of said first transistor and said base of said third transistor; a first resistor connected between said emitter of said first transistor and a second source of potential; a second resistor connected between said first sourc