Abstract: A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.

Abstract: A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field.

Abstract: A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field.

Abstract: A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart.

Abstract: A voltage regulator employs a PNP output transistor of vertical construction, which operates as a linear control element in a feedback controlled circuit which is formed in a substrate. A differential amplifier has one input coupled to a voltage reference and another input coupled via feedback from a resistive voltage divider connected between common and the output of the voltage regulator. A parasitic NPN transistor, which is merged physically and thermally with the structure of the PNP output transistor, senses the onset of output transistor saturation and re-routes the majority of the excess base current drive to a feedback control node. The feedback control node retards total excess drive via a reduction in drive amplifier gain and bandwidth thereby assuring good stability of feedback loop operation during all phases of saturation, without the need for additional frequency compensating elements.

Abstract: In a non-inverting gain stage of the type that receives a single input and generates a single-ended output, the improvement comprising a feed-forward path which provides the input to the output when the supply is above a preselected frequency. The stage is capable of operation down to very low supply voltage (1V) and features rail-to-rail ouput swing.

Abstract: A high speed buffer circuit is composed of complementary symmetry emitter follower driver and output stages. The input of driver stage includes active load devices cross-coupled to the output stage inputs so that the output stage is bootstrap driven from emitter followers. The circuit is biased by level shifting means to operate as a class AB current amplifier. It displays a wide bandwidth along with a high slew rate and can source or sink a large pulsed current.

Abstract: A peaking capacitor for use with a differential input stage in an integrated circuit. The stage includes emitter degeneration resistors and a peaking capacitor coupled between the emitters. The capacitor is formed of MOS capacitors located over thinned oxide portions that lie within the confines of doped regions forming PN junctions with the semiconductor substrate. The doped regions are spaced apart by a distance that will result in depletion region reach-through at a voltage that is lower than the thinned oxide breakdown voltage. Thus, the structure is self-protecting and therefore resistant to electrostatic discharge damage. The capacitor that is formed has a value that is determined accurately by the area of the thinned oxide. It also has a low stray capacitance which makes it useful as a peaking capacitor.

Abstract: An integrated circuit voltage follower buffer amplifier is provided with a feedback capacitor that is coupled to produce positive feedback current that acts to enhance slew rate. In an op amp a polarity sensitive slew rate enhancement acts to correct slew rate asymmetry. Circuits are shown for avoiding assymetry or boosting slew rate of both polarities. In all cases, the positive feedback current is made proportional to the rate of change of the output voltage.

Abstract: In a CMOS structure a pair of BJTs are provided with lateral collectors and operated at different current densities. The lateral collectors are coupled to a current mirror load which provides a single ended output node. The pair bases are coupled together and to the current mirror load input so that the lateral BJT collectors operate at low potential. A current source supplies tail current and a resistor is coupled in series with the low current density BJT. The single ended output node is coupled to a current mirror that determines the BJT tail current. The circuit therefore has a negative feedback loop around the BJTs that will stabilize operation so that .DELTA.V.sub.BE appears across the resistor. The resistor can be chosen so that the overall circuit temperature coefficient can be established at a desired value.

Abstract: An output stage is disclosed wherein class AB bias is employed. The stage is quiescently biased by means of current mirrors so that the bias is controlled mainly by ratioed geometric elements. The output transistors are biased by means of unity gain common gate drivers that provide the desired level shifting. The output voltage can be swung from from close to the rail potential of the source of the n channel output transistor to close to the rail potential of the source of the p channel transistor. The circuit can drive relatively large load currents and can be fabricated using either CMOS or conventional bipolar integrated circuits.

Abstract: A Darlington output stage is shown in which the saturation voltage is substantially reduced by the incorporation of a complementary transistor. An IC form of the circuit is shown in detail.

Abstract: An integrated circuit buffer inverter is created by cascading an emitter follower stage with a common emitter stage. Both stages include constant collector current loads. The emitter follower stage is adaptively biased from a current mirror that is driven from the collector of the emitter follower for the purpose of maximizing bipolar drive to the common emitter stage.

Abstract: An emitter coupled oscillator having a wide bandwidth capability is tuned by an applied voltage or current. The oscillator obtains its feedback coupling by means of a differential amplifier which greatly reduces the second order temperature versus frequency drift. This is accomplished by forcing the oscillator to trip under conditions which greatly reduce V.sub.BE in the switching transistors.

Abstract: A carrier current receiver employs a comparator driven differentially to square a received data signal. The same drive signal is applied to a sample and hold circuit in which a capacitor is charged to a level that is related to the data signal offset. A voltage-to-current converter responds to the capacitor charge and feeds a current to the input where it acts to correct the offset.

Abstract: An amplifier suitable for carrier current line driver applications is shown. It includes a triangle wave to sine wave shaper circuit and an automatic level control. It incorporates a line surge arrestor circuit that is active even when the transmitting capability is disabled. The circuit is shown in an integrated circuit form, the output of which is capable of being boosted by off-chip components.

Abstract: A trigger circuit with hysteresis is created by driving a latch circuit set and reset terminals through a pair of emitter driven complementary transistors the bases of which are returned to a reference potential V.sub.REF. The hysteresis is set by the V.sub.BE potentials of the complementary transistors. When the input emitters are driven more than one V.sub.BE above V.sub.REF, one transistor will conduct and set the latch. When the input falls below one V.sub.BE below V.sub.REF, the other transistor will conduct and reset the latch. A digital filter is created by coupling a capacitor across the trigger circuit input and digitally driving the capacitor through a transconductance amplifier.

Abstract: A communication system for providing both analog information pulses and digital information pulses in a single frame of a pulse train, including circuitry for sequentially multiplexing and modulating a first given number "m" of analog information input channels to provide "m" analog information pulses in each frame of the pulse train to convey information respectively representative of the analog information in the analog information input channels; and circuitry for modulating a second given number "n" of binary information input channels to provide a variable number of digital information pulses and for multiplexing the variable number of digital information pulses in each frame of the pulse train sequentially to the analog information pulses, wherein the variable number of digital information pulses is within a range of 2.sup.n pulses to convey information respectively representative of the binary information in the "n" binary information input channels.

Abstract: An integrated circuit is employed to provide a high gain signal amplifier having an automatic gain control function and an output suitable for driving signal detection circuitry in a radio receiver. The circuit operates at the receiver intermediate frequency. A gain controlled cascode amplifier drives one input of a high gain differential amplifier. The other input is returned to a reference potential. A pair of current mirrors are coupled into the differential amplifier to provide a pair of single ended outputs. One output drives a peak rectifying diode to operate the automatic gain control and the other output drives a signal detection circuit. The current mirrors are ratioed so that the automatic gain control threshold is a predetermined fixed multiple of the signal threshold.

Abstract: A three terminal current gain cell is made up of a three-stage common emitter high gain amplifier configuration using complementary transistors. A controlled percentage of the output is coupled back to the input to provide negative feedback. The emitters of the complementary devices are coupled to the appropriate terminals that comprise the cell output. One of the devices employs a dual ratioed collector with the smaller of the two collectors being made to track the input current due to the feedback condition. Thus, the current gain of the cell is determined by a geometric ratio. The gain can be further multiplied by employing additional ratioed devices within the cell or by cell cascading. In one application, the current gain cell is combined with a photo sensor providing the input current. This produces a two terminal device that passes a current linearly related only to the illumination level over a very large range of illumination and other ambient conditions.