Patents by Inventor Denzil S. Frost
Denzil S. Frost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784077Abstract: A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.Type: GrantFiled: December 18, 2019Date of Patent: October 10, 2023Assignee: Micron Technology, Inc.Inventors: Denzil S. Frost, Richard T. Housley, David S. Pratt, Trupti D. Gawai
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Patent number: 11424291Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.Type: GrantFiled: December 21, 2017Date of Patent: August 23, 2022Assignee: Micron Technology, Inc.Inventors: Denzil S. Frost, Tuman Earl Allen, III
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Patent number: 11075169Abstract: A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.Type: GrantFiled: December 19, 2018Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Denzil S. Frost, Richard T. Housley, Jianming Zhou
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Publication number: 20210193493Abstract: A method for determining overlay measurements includes orienting a wafer to align portions of lines of a pattern of an overlay mark with a direction in which a source emits light at the wafer and align other portions of the lines of the pattern to extend in a direction perpendicular to the direction in which the illumination source emits light at the wafer. The method includes capturing at least one image of the wafer via an imager sensor. The method also includes determining contrasts of regions of the overlay mark and determining a location of the overlay mark. Overlay marks include a pattern defining an array of columns. Each column includes a set of continuous lines oriented parallel to each other and extending in a first direction within a first region of a column and extending in a second different direction in a second region of the column.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Inventors: Denzil S. Frost, Richard T. Housley, David S. Pratt, Trupti D. Gawai
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Publication number: 20200203284Abstract: A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Applicant: Micron Technology, Inc.Inventors: Denzil S. Frost, Richard T. Housley, Jianming Zhou
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Patent number: 10629652Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: GrantFiled: November 15, 2018Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
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Publication number: 20190206942Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 15, 2018Publication date: July 4, 2019Inventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
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Patent number: 10134809Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: GrantFiled: June 2, 2017Date of Patent: November 20, 2018Assignee: INTEL CORPORATIONInventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
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Publication number: 20180122858Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.Type: ApplicationFiled: December 21, 2017Publication date: May 3, 2018Inventors: Denzil S. Frost, Tuman Earl Allen, III
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Patent number: 9881972Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.Type: GrantFiled: May 20, 2016Date of Patent: January 30, 2018Assignee: Micron Technology, Inc.Inventors: Denzil S. Frost, Tuman Earl Allen, III
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Publication number: 20170338280Abstract: A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Inventors: Denzil S. Frost, Tuman Earl Allen, III
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Publication number: 20170271412Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Inventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
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Patent number: 9704923Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: GrantFiled: December 23, 2015Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer
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Publication number: 20170186815Abstract: Embodiments of the present disclosure describe techniques and configurations for a memory device comprising a memory array having a plurality of wordlines disposed in a memory region of a die. Fill regions may be disposed between respective pairs of adjacent wordlines of the plurality of wordlines. The fill regions may include a first dielectric layer and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer may comprise organic (e.g., carbon-based) spin-on dielectric material (CSOD). The second dielectric layer may comprise a different dielectric material than the first dielectric layer, such as, for example, inorganic dielectric material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Michael J. Bernhardt, Yudong Kim, Denzil S. Frost, Tuman Earl Allen, III, Kevin Lee Baker, Kolya Yastrebenetsky, Ronald Allen Weimer