Patents by Inventor DerChang Kau

DerChang Kau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475853
    Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jong-Won Lee, Gianpaolo Spadini, Stephen W. Russell, Derchang Kau
  • Publication number: 20190339585
    Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a substrate, a waveguide disposed above the substrate, a phase change layer disposed above the waveguide, and a heater disposed above the phase change layer. The waveguide has a modifiable refractive index based at least in part on a state of a phase change material included in the phase change layer. The phase change material of the phase change layer is in a first state of a set of states, and the waveguide has a first refractive index determined based on the first state of the phase change material. The heater is to generate heat to transform the phase change material to a second state of the set of states, and the waveguide has a second refractive index determined based on the second state of the phase change material. Other embodiments may also be described and claimed.
    Type: Application
    Filed: July 19, 2019
    Publication date: November 7, 2019
    Inventors: John Heck, Harel Frish, Derchang Kau, Charles Dennison, Haisheng Rong, Jeffrey Driscoll, Jonathan K. Doylend, George A. Ghiurcan, Michael E. Favaro
  • Publication number: 20190332278
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Application
    Filed: May 31, 2019
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10431270
    Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Publication number: 20190259453
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Patent number: 10331360
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10304534
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Publication number: 20190096484
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: November 21, 2018
    Publication date: March 28, 2019
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Publication number: 20190013358
    Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 10, 2019
    Inventors: Jong-Won Lee, Gianpaolo Spadini, Stephen W. Russell, Derchang Kau
  • Patent number: 10163507
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Patent number: 10163982
    Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Fabio Pellizzer, Agostino Pirovano, DerChang Kau
  • Publication number: 20180366196
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 20, 2018
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Publication number: 20180286921
    Abstract: Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Andrea REDAELLI, Innocenzo TORTORELLI, Fabio PELLIZZER, Agostino PIROVANO, DerChang KAU
  • Patent number: 10090050
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Patent number: 10050084
    Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 14, 2018
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Jong-Won Lee, Gianpaolo Spadini, Stephen W. Russell, Derchang Kau
  • Publication number: 20180182457
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 28, 2018
    Inventors: DerChang Kau, Gianpaolo Spadini
  • Publication number: 20180151206
    Abstract: Apparatuses for increasing the voltage budget window of a memory array are described. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Publication number: 20180088834
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Applicant: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 9905280
    Abstract: Methods and apparatuses for increasing the voltage budget window of a memory array are disclosed. One or more pre-bias voltages may be applied across a selected cell by providing voltages to memory access lines coupled to the selected cell. The threshold voltage of the selected cell may decrease responsive to the pre-bias voltage. Conversely, threshold voltage of deselected cells coupled to only one of the memory access lines coupled to the selected cell may increase responsive to the pre-bias voltage. The decrease of the threshold voltage of the selected cell and the increase of the threshold voltage of the deselected cells may increase the voltage window of the memory array.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Davide Mantegazza, Kiran Pangal, Feng Q. Pan, Hernan A. Castro, DerChang Kau
  • Patent number: 9905296
    Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: DerChang Kau, Gianpaolo Spadini