Abstract: A differential input/differential output OTA includes two resistively degenerated matched pairs of bipolar transistors; one pair provides differential input, the other provides differential output and feedback to the first pair, thus canceling AC distortions. In voltage controlled filter applications that employ the new OTA, control feedthrough is significantly reduced when compared to similar low pass filters which employ conventional OTAs.

Abstract: A bipolar transistor current mirror circuit has the bases of its input and output transistors connected together, but decouples the input transistor's collector from its base so that the mirror input voltage is no longer tied to the input transistor's base-emitter voltage. Instead, a separate base current source supplies sufficient base current to the mirror's input transistor to keep it in saturation, while a parasitic transistor that results from a junction isolated fabrication process drains off excess current from the base current source to keep it in balance with the mirror transistor base currents. The resulting input voltage is a function of the input transistor's saturated collector-emitter voltage, which is substantially lower than the base-emitter voltage and provides more voltage head room.

Abstract: A three state logic input recognizes three logic levels: an intermediate level in addition to the conventional "high" and "low" levels employed by binary logic systems. The three state device may be used in purely ternary logic systems or in "hybrid" systems which combine binary and ternary logic. In a preferred embodiment, the new three state logic device comprises a "passive driver" which is connected to produce one of three predetermined logic levels in corresponding to impedance paths from its input terminal through an external circuit to a positive or negative voltage supply. In hybrid ternary/binary applications, the new three state input device includes a decoder that is connected to decode the three predetermined logic levels provided by the passive driver into binary logic for use by associated binary logic devices. In a digital to analog converter application, the three state input device is employed to recognize both a binary logic and a control signal at one input pin to the DAC.

Abstract: A guard ring with the same conductivity as a device pocket surrounds the pocket and a pocket isolation ring to establish a parasitic transistor that conducts current between the guard ring and the pocket when the pocket voltage is driven sufficiently below the substrate voltage. The guard ring is connected to a voltage supply for the circuit which, together with its shorter current path, allows the parasitic transistor to harmlessly divert current away from unwanted inter-pocket parasitic transistors.

Abstract: A comparator combines unbalanced differential input amplifiers to produce a balanced input stage that forces the comparator output to a predetermined state whenever the first differential amplifier enters dropout. The comparator's second differential amplifier is imbalanced to overcome the variable offset voltage which creates the comparator's hysteresis voltage. Its first differential amplifier is imbalanced to compensate for the imbalance of the second amplifier, thereby producing an input stage which is balanced overall and free of input offset voltages that would otherwise be present.

Abstract: A wide-band voltage controlled amplifier includes a differential stage and a gain control stage. The differential stage responds to a differential input signal by apportioning a bias current between the two sides of the differential stage. The gain control stage responds to a variable gain control voltage by further dividing the current in each side of the differential stage to set the gain of the VCA. The negative resistance circuit is connected across the differential stage to supply a correction current that reduces the non-linearity distortion in the current supplied to the gain control stage, which in turn improves the linearity of the VCA's output voltage.

Abstract: A CMOS input circuit that has a first inverter stage for comparing non rail-to-rail digital input voltages to a threshold voltage, and producing inverted CMOS output voltages is disclosed. The inverted output voltages are approximately equal to a low CMOS supply voltage plus an offset voltage and a high CMOS supply voltage. The inverter includes PMOS and NMOS transistors that are connected to receive a common input voltage at their gates and to have a common drain current. The PMOS' source is connected to the high supply voltage, and the NMOS' source is connected through a voltage drop circuit element to the low supply voltage. The inverted output voltage is produced at the connection of the PMOS and NMOS transistors' drains. The NMOS and PMOS transistors have gate width and length parameters W.sub.N, L.sub.N and W.sub.P, L.sub.P, respectively. The ratio ##EQU1## is selected so that the threshold voltage is set between the maximum low and minimum high input signals for a desired range of high supply voltages.

Abstract: An operational amplifier input circuit for preventing phase reversal and maintaining performance for inputs outside the common mode range includes a pair of differentially connected transistors for receiving respective differential inputs, and a folded cascode pair of transistors that are coupled to the differential transistors. A pair of resistors are connected between a reference potential and the current circuits of the differential and cascode transistors to produce resistor voltages that control the respective cascode transistors' currents. The differential transistors respond to an input by producing a forward biased parasitic diode in one of the differential transistors. A phase compensation circuit responds to the input by shifting the resistor voltage for the other differential transistor to prevent a phase reversal of the resistor voltages.

Abstract: A analog-to-digital converter (DAC) comprises a plurality of circuit stages. Each of the circuit stages includes a switching circuit having an assertive circuit portion and a complementary circuit portion. A first transistor and a first resistor constitute the assertive circuit portion, which is electrically connected between a first reference voltage supply conductor and a switch output node inside the DAC. In a similar fashion, a second transistor and a second resistor constitute the complementary circuit portion, which is also electrically connected between a second reference voltage supply conductor and the switch--output node. The first and second resistors, and the resistor in the resistor network which is electrically connected to the switch output node, are substantially equal in ohmic values.

Abstract: Charging of parasitic capacitances present in a unity gain buffer amplifier is speeded up, with a consequent increase in input slew rate capability, by connecting a resistance circuit across the current sources and output transistors. Imbalances in the response rate of the input transistors to changes in the input voltage produce a current shift through the resistor that charges parasitic capacitances to speed up the output transistor response.

Abstract: An audio sound system decodes from non-encoded two-channel stereo into at least four channel sound. The rear channel information is derived by taking a difference of left minus right and dividing that difference into a plurality of bands. In a simplistic implementation, at least one band is dynamically steered while the other band is unaltered so as to avoid any perceived pumping effects while providing transient information to left/right, as well as directional enhancement. In a preferred embodiment, multiple bands are dynamically steered left or right, so as to enhance directional information to the rear of the listener. In both schemes, the low pass filtered output of the sum of the left and right inputs is also combined with the directionally enhanced information, so as to provide a composite left rear and right rear output.

Abstract: A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for the NPN transistor. A buried P diffusion provides "up" isolation for the NPN transistor and buried collector for the PNP transistor. A method for increasing the NPN buried collector to "up" isolation breakdown voltage is described which uses multiple N type impurities.

Abstract: The output stage for a feedback amplifier has a diode circuit to provide quiescent current to the output transistors, and a diode turnoff circuit that renders the diodes non-conductive for an input signal that sends the stage output voltage low. A swing transistor between the stage's output terminal and a low voltage bus is actuated by the same input signal to drive the output voltage to the level of the low voltage bus. Both the diode turnoff circuit and the swing transistor are preferably MOSFETs.

Abstract: A first Schottky diode is connected between the source of a first enhancement JFET and a low voltage line. The drain of the first enhancement JFET is connected through a first active load current source to a high voltage line, and also through a second Schottky diode and a second active load current source to the low voltage line. The first Schottky diode produces a voltage drop which maintains the source of the first enhancement JFET positive with respect to the low voltage line. The second Schottky diode produces a voltage drop complementary to that of the first Schottky diode, which causes the circuit to produce an output voltage across the second current source having a logically low level close to that of the low voltage line.

Abstract: A new instrumentation amplifier design uses three operational amplifiers (op amps), each of which has a feedback circuit connected from its output to its inverting input. The first op amp has a unity gain feedback, and is connected through a gain setting resistor to the inverting input of the second op amp. The output of the third op amp is connected through a resistor to the inverting input for the second op amp, while the third op amp's non-inverting input is connected to one of the second op amp's inputs. Differential voltage input signals are applied to the non-inverting inputs of the first and second op amps, while a reference voltage is applied to the inverting input of the third op amp. The circuit is capable of operating with a single voltage supply (V+) by setting the negative voltage supply together with the reference voltage at ground potential. It has a simplified gain equation based upon the ratio between the feedback resistor for the second op amp and the gain setting resistor.

Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from a nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from the nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.

Abstract: A three-terminal operational amplifier includes a current input, in addition to the conventional inverting and non-inverting inputs. The current input is inverted and added to the inverting input current, while its voltage is urged to a level equal to that of the inverting and non-inverting inputs. The new amplifier employs a pair of two-terminal operational amplifiers, the first of which has inverting and non-inverting inputs, and the second of which has the current input and a second input connected in common with an input to the first amplifier. Internal feedback circuits provide the desired current conveyance. The circuit may be implemented either with mutually discrete two-terminal operational amplifiers, or these elements may be merged into a single unified circuit. Applications include a general purpose adder/subtractor circuit, an inverting gain amplifier, an instrumentation amplifier, integrators and differentiators.

Abstract: A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.

Abstract: A digital-to-analog converter (DAC) ladder segment is disclosed in which diode networks are introduced into the ladder step circuits. Each diode network includes a control diode which controls the flow of current through the network in accordance with a signal from an associated actuating circuit, which in turn is controlled by an input digital signal. In one embodiment, the control diodes are connected in series with resistors, with the diodes and resistors scaled so that their respective bit circuits conduct desired current levels. In another embodiment, the control diodes have equal scalings and are connected in series with respective resistors and second diodes which are called so that their step circuits conduct the desired currents. In a third embodiment, current sources are provided which supply currents to the second diodes in amounts that permit the second diode and the resistors for the various step circuits to have substantially equal scalings.