Patents by Inventor Derek F. Bowers

Derek F. Bowers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4757274
    Abstract: An improved input current compensation circuit is provided for a dual branch amplifier, particularly an amplifier employing superbeta transistors. The compensation circuit has a superbeta compensation transistor which is matched with the superbeta amplifier transistors, a bipolar transistor connected across the superbeta transistor in a manner analogous to a voltage limiting circuit in the amplifier section, and current sources which provide operating currents to both the superbeta and bipolar compensation transistors. The base current of the superbeta compensation transistor is mirrored to the bases of the superbeta amplifier transistors, and the superbeta transistors, bipolar transistor and current sources in the compensation section are scaled relative to corresponding elements in the amplifier section so that the superbeta amplifier transistor base currents are substantially compensated by current mirrored from the compensation circuit.
    Type: Grant
    Filed: January 14, 1987
    Date of Patent: July 12, 1988
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4677369
    Abstract: A temperature insensitive voltage reference is described which can advantageously be implemented using standard CMOS processing techniques. A pair of parasitic bipolar transistors are coupled with appropriate resistors to produce a voltage with a temperature coefficient that is equal in value but of opposite polarity to a zener diode voltage-temperature coefficient. This voltage is then combined with a zener diode voltage to yield the desired output reference voltage.
    Type: Grant
    Filed: September 19, 1985
    Date of Patent: June 30, 1987
    Assignee: Precision Monolithics, Inc.
    Inventors: Derek F. Bowers, Ali Tasdighi
  • Patent number: 4675561
    Abstract: A CMOS output drive circuit has two field effect transistors (FETs) implemented with a CMOS process and characterized by parasitic bipolar transistors. The back-gates of the two transistors are tied together, such as by forming the devices in a common well, and the back-gate of the second FET is also connected to prevent its associated parasitic bipolar transistor from conducting. Quiescent loads are applied to the two FETs so that their voltages are comparable during low output loading, resulting in a drive circuit with high input impedance and high output voltage swing. The output terminal is taken from the first FET, the voltage of which becomes unbalanced from the second FET at relatively high output loads, turning on the parasitic bipolar transistor for the first FET. This gives the drive circuit a desirably high input impedance and low output impedance for heavy output loads.
    Type: Grant
    Filed: November 15, 1985
    Date of Patent: June 23, 1987
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4633165
    Abstract: A temperature compensated voltage reference circuit in which a compensation current is generated by establishing a current through a passive impedance element which varies with temperature in accordance with the transistor voltage equation. This current is proportionately reflected into the output impedance circuit associated with the voltage reference, where it compensates for temperature induced voltage variations. The passive impedance element is adjustable to correct for processing variations, and the compensation circuit requires no voltage supplies other than those typically provided for the reference circuit by itself.
    Type: Grant
    Filed: August 15, 1984
    Date of Patent: December 30, 1986
    Assignee: Precision Monolithics, Inc.
    Inventors: Steven M. Pietkiewicz, Derek F. Bowers
  • Patent number: 4583051
    Abstract: An output circuit amplifier has first and second stage amplifying transistors with an impedance circuit connected between the base of the first stage transistor and the collector-emitter circuit of the second stage transistor to draw current from the first stage transistor base, thereby keeping both transistors out of saturation. The impedance circuit establishes a voltage drop between the two transistors such that large output voltage swings are enabled at an output terminal connected to the second stage transistor. The collector-emitter circuit of the first stage transistor is connected directly to a positive voltage bus to avoid further saturation problems.
    Type: Grant
    Filed: November 6, 1984
    Date of Patent: April 15, 1986
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4572975
    Abstract: An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal.
    Type: Grant
    Filed: April 2, 1984
    Date of Patent: February 25, 1986
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4503381
    Abstract: An integrated current mirror circuit in which a compensation transistor is added in each stage of the mirror to compensate for the base-substrate leakage currents of the other transistors in the mirror circuit and to keep the circuit operative even at high temperatures and low current levels. Each compensation transistor is matched with the other transistors in its stage and has its collector-emitter circuit connected between a voltage source terminal and the common base connection of the other transistors. The base of each compensation transistor is unconnected to the remainder of the circuit but exhibits a base-substrate leakage current which is employed in the compensation scheme.
    Type: Grant
    Filed: March 7, 1983
    Date of Patent: March 5, 1985
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers
  • Patent number: 4471321
    Abstract: An improved input current compensation circuit is provided for a superbeta transistor amplifier. The circuit has a pair of compensation transistors which simulate the amplifier transistors and support a base current which is mirrored back to the amplifier circuit to cancel the input currents thereof. The compensation transistors are supplied with base current by a control transistor. A special voltage control circuit is provided to establish controlled collector-emitter voltages for the compensation transistors independent of the control transistor, thereby decoupling the compensation transistors from the uncertain effects of the control transistor's base-emitter voltage. The control circuit is connected from the collector of one compensation transistor to the emitter of the other, and is provided with primary and secondary current sources to establish a current flow that sets up a desired bias for the control transistor and results in a near exact cancellation of input bias current.
    Type: Grant
    Filed: December 17, 1982
    Date of Patent: September 11, 1984
    Assignee: Precision Monolithics, Inc.
    Inventor: Derek F. Bowers