Patents by Inventor Derryl Allman

Derryl Allman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6891219
    Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 10, 2005
    Assignee: LSI Logic Corporation
    Inventors: Derryl Allman, John Gregory
  • Patent number: 6861310
    Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: March 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Derryl Allman
  • Publication number: 20050015651
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. The test vehicle incorporates a self-timed or gated speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program data logs from scan flip flops. One embodiment incorporates a gated clock in the gated speed circuit producing gated data that delivers greater statistical properties with respect to Integrated Circuit Direct Drain Quiescent Current (IDDQ) testing.
    Type: Application
    Filed: July 27, 2004
    Publication date: January 20, 2005
    Inventors: Richard Schultz, Derryl Allman, Jan Fure
  • Publication number: 20050003562
    Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
    Type: Application
    Filed: July 2, 2003
    Publication date: January 6, 2005
    Inventors: Hemanshu Bhatt, Jan Fure, Derryl Allman
  • Patent number: 6743701
    Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: June 1, 2004
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Steven E. Reder, Derryl Allman
  • Publication number: 20030113967
    Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
    Type: Application
    Filed: November 26, 2002
    Publication date: June 19, 2003
    Inventors: Derryl Allman, John Gregory
  • Patent number: 6524926
    Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: February 25, 2003
    Assignee: LSI Logic Corporation
    Inventors: Derryl Allman, John Gregory
  • Publication number: 20030006447
    Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.
    Type: Application
    Filed: August 27, 2002
    Publication date: January 9, 2003
    Applicant: LSI Logic Corporation
    Inventor: Derryl Allman
  • Patent number: 6479857
    Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 12, 2002
    Assignee: LSI Logic Corporation
    Inventor: Derryl Allman
  • Patent number: 6071562
    Abstract: The present invention provides an efficient process for depositing a titanium nitride film on a substrate. The process comprises the steps of heating the substrate and subsequently exposing the heated substrate to a first gas containing tetrakis(dimethylamido)titanium and to a second gas containing tetrakis(diethylamido)titanium.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: June 6, 2000
    Assignee: LSI Logic Corporation
    Inventors: Verne Hornback, Derryl Allman