Abstract: An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C.

Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.

Abstract: The invention concerns the use of spin-on-glass (SOG) to bond two layers of semiconductor together, in order to form a Silicon-on-Insulator (SOI) structure. One type of SOG is a cross-linked siloxane polymer, preferably of the poly-organo-siloxane type, comprising a carbon content of at least 5 atomic weight percent.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: Control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved, in a first embodiment, by adding, to the carbon-substituted silane reactant, silane (SiH4), to accelerate the process for forming a low k carbon-containing silicon oxide dielectric material by reaction of the carbon-substituted silane/silane mixture with hydrogen peroxide. Also, control of a reaction between a peroxide oxidizing agent and a carbon-substituted silane to form a low k carbon-containing silicon oxide dielectric material is achieved by controlling the ratio of the flow of the hydrogen peroxide reactant and the flow of the reactant mixture of carbon-substituted silane and unsubstituted silane into the reaction chamber though structural modification of the faceplate (showerhead) through which the reactants flow into the chamber.

Abstract: A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing the photoresist mask in a plasma reactor to a plasma formed using a reducing gas until the photoresist mask is removed. In a preferred embodiment the reducing gas is selected from the group consisting of NH3, H2, forming gas, and a mixture of NH3 and H2.

Abstract: A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

Abstract: An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track.

Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.

Abstract: A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

Abstract: A process for forming a conductive via in an integrated circuit structure that includes a first dielectric layer overlying a first conductive layer. A via cavity is formed in the first dielectric layer, which exposes the first conductive layer. A titanium nitride liner layer is formed in the via cavity, and the titanium nitride liner layer is exposed to an isotropic plasma containing hydrogen ions, thereby densifying the liner layer. A second conductive layer is formed adjacent the titanium nitride liner layer in the via cavity, which second conductive layer substantially fills the via cavity to form the conductive via. The via cavity is selectively etched with a hydrogen containing plasma prior to forming the titanium nitride liner layer. The plasma etch at least partially removes residue in the bottom of the via cavity, including carbon and oxygen.

Abstract: An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.

Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.