Patents by Inventor Desmond J. Donegan, JR.

Desmond J. Donegan, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9041119
    Abstract: A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 26, 2015
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Desmond J. Donegan, Jr., Abhishek Dube, Steven Jones, Jophy S. Koshy, Viorel Ontalus
  • Publication number: 20130295740
    Abstract: A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Desmond J. Donegan, JR., Abhishek Dube, Steven Jones, JOPHY S. KOSHY, Viorel Ontalus