Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer.

Abstract: The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

Abstract: A non-volatile memory device and method of making the same is provided. The memory device includes a first electrode, a first hard mask on the first electrode, a second electrode on the first hard mask, a second hard mask on the second electrode, and a third electrode on the second hard mask. A switching layer is over the electrode stack and the switching layer has a first portion conformal to the side surfaces of the electrode stack.

Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.

Abstract: A memory device and method of making the same is provided. The memory device includes a first electrode, an oxygen scavenging layer on the first electrode, a hard mask on the oxygen scavenging layer, and a second electrode on the hard mask. A switching layer is arranged on a portion of the oxygen scavenging layer, and the switching layer is conformal to a side surface of the hard mask.

Abstract: The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices with an electrode having tapered sides. The present disclosure provides a memory device including a first electrode having a tapered shape and including a tapered side, a top surface, and a bottom surface, in which the bottom surface has a larger surface area than the top surface, a resistive layer on and conforming to at least the tapered side of the first electrode, and a second electrode laterally adjacent to the tapered side of the first electrode, the second electrode including a top surface and a side surface abutting the resistive layer, in which the side surface forms an acute angle with the top surface.

Abstract: A memory device may be provided, including a base insulating layer, a bottom electrode arranged within the base insulating layer, a substantially planar switching layer arranged over the base insulating layer and a substantially planar top electrode arranged over the switching layer in a laterally offset position relative to the bottom electrode.

Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: The present disclosure generally relates to structures, memory devices, and a method of forming the same. The structures and the memory devices may include a first electrode, a first oxygen scavenging layer disposed upon the first electrode, a resistive layer disposed upon the first oxygen scavenging layer, a second oxygen scavenging layer disposed upon the resistive layer, and a second electrode disposed upon the second oxygen scavenging layer. The structures and the memory devices may reduce the switching voltage or switching current for bidirectional switching of the resistive layer.

Abstract: A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

Abstract: The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer, a first electrode, and a second electrode. The first switching layer includes a portion positioned between the first electrode and the conductive spacer, the second switching layer includes a portion positioned between the second electrode and the conductive spacer, and the conductive spacer is positioned between the portion of the first switching layer and the portion of the second switching layer.

Abstract: Structures for a non-volatile memory and methods of forming and using such structures. A resistive memory element includes a first electrode, a second electrode, and a switching layer arranged between the first electrode and the second electrode. A transistor includes a drain coupled with the second electrode. The switching layer has a top surface, and the first electrode is arranged on a first portion of the top surface of the switching layer. A hardmask, which is composed of a dielectric material, is arranged on a second portion of the top surface of the switching layer.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure also relates to a method of forming such semiconductor devices. The disclosed semiconductor devices may achieve a smaller cell size as compared to conventional devices, and therefore increases the packing density of the disclosed devices.

Abstract: A memory device may be provided, including a first electrode, an insulating element arranged over the first electrode, a second electrode arranged over the insulating element, a switching layer and a conductive line electrically coupled to the second electrode. Each of the first electrode, the insulating element, and the second electrode may include a first side surface and a second side surface. Centers of the first electrode, the insulating element, and the second electrode may be substantially vertically aligned. The first side surface and the second side surface of the second electrode may be substantially vertically aligned with the first side surface and the second side surface of at least one of the insulating element and the first electrode. The switching layer may be conformal to the first side surfaces and the second side surfaces of the second electrode and the insulating element.

Abstract: Structures including non-volatile memory elements and methods of fabricating a structure including non-volatile memory elements. First, second, and third non-volatile memory elements each include a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. A first bit line is coupled to the first electrode of the first non-volatile memory element and to the first electrode of the second non-volatile memory element. A second bit line is coupled to the first electrode of the third non-volatile memory element.

Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer.