Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A method for depositing a monocrystalline semiconductor layer consisting of a first element and a second element, wherein the first elements is fed as part of a hydride, and the second element is fed as part of a halide, together with a carrier gas, into a process chamber of a reactor, wherein radicals are produced from the hydride at a distance away from a surface of a semiconductor substrate, wherein at a temperature below a decomposition temperature of the radicals, at a total pressure of the gas in the process chamber sufficiently low to avoid a reverse reaction of the radicals in the gas phase the radicals and the halide are brought to the surface of the semiconductor substrate which is heated to a substrate temperature lower than the decomposition temperature, wherein heat released during a first exothermic chemical reaction drives a second endothermic chemical reaction.

Abstract: A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm?2, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as Ge2H6 or Si2H6; providing a halide of a second IV element (B), such as SnCl4; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.

Abstract: A method for producing a planar free surface comprising embedded, contactable nanostructures includes arranging at least one nanostructure on a surface of an initial substrate; applying a first layer to the surface of the initial substrate, wherein the first layer embeds the at least one nanostructure; applying a target substrate to the first layer; and separating the initial substrate from the first layer such that the at least one nanostructure embedded in the first layer has a planar free surface. An additional layer is applied to the surface of the initial substrate before the at least one nanostructure is applied to the initial substrate, and in that the initial substrate is removed from the first layer using a solvent.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A method for producing a planar free surface comprising embedded, contactable nanostructures includes arranging at least one nanostructure on a surface of an initial substrate; applying a first layer to the surface of the initial substrate, wherein the first layer embeds the at least one nanostructure; applying a target substrate to the first layer; and separating the initial substrate from the first layer such that the at least one nanostructure embedded in the first layer has a planar free surface. An additional layer is applied to the surface of the initial substrate before the at least one nanostructure is applied to the initial substrate, and in that the initial substrate is removed from the first layer using a solvent.

Abstract: A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces of the base material permeable by a current to the total volume of the base material is increased by a) dividing the base material perpendicularly to the direction of current into at least two segments, which are spaced from each other by an electrically conductive intermediate piece and connected both electrically and mechanically to each other, and/or b) topographical structures in or on the surface of the base material and/or c) inner porosity of at least a portion of the base material compared to a design of the base material in which the respective feature was omitted.

Abstract: A method for monolithically depositing a monocrystalline IV-IV layer that glows when excited and that is composed of a plurality of elements of the IV main group, in particular a GeSn or Si—GeSn layer, the IV-IV layer having a dislocation density less than 6 cm?2, on an IV substrate, in particular a silicon or germanium substrate, including the following steps: providing a hydride of a first IV element (A), such as Ge2H6 or Si2H6; providing a halide of a second IV element (B), such as SnCl4; heating the substrate to a substrate temperature that is less than the decomposition temperature of the pure hydride or of a radical formed therefrom and is sufficiently high that atoms of the first element (A) and of the second element (B) are integrated into the surface in crystalline order, wherein the substrate temperature lies, in particular, in a range between 300° C. and 475° C.

Abstract: A high-frequency conductor having improved conductivity comprises at least one electrically conductive base material. The ratio of the outer and inner surfaces of the base material permeable by a current to the total volume of the base material is increased by a) dividing the base material perpendicularly to the direction of current into at least two segments, which are spaced from each other by an electrically conductive intermediate piece and connected both electrically and mechanically to each other, and/or b) topographical structures in or on the surface of the base material and/or e) inner porosity of at least a portion of the base material compared to a design of the base material in which the respective feature was omitted.

Abstract: A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.

Abstract: A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.

Abstract: Method for making a semiconductor structure is proposed. It comprises the steps: —providing a base layer (10) having a first lattice constant, —forming buried islands on the base layer (10) having a second lattice constant that is smaller or larger than the first lattice constant, —at least partially covering the base layer (10) and the buried islands with a cover layer (14), whereby the cover layer (14) has a locally increased or reduced lattice constant in areas above the buried islands, —growing small islands (15) on the areas of the cover layer (14) with locally increased or reduced lattice constant, —depositing a thin layer (16) at least partially covering the cover layer (14) and the small islands (15), —at least partially removing the small islands (15) to provide for an opening (17) being positioned exactly above the buried islands.

Abstract: This invention relates to a device for emitting addressable locations comprises parallel spaced-apart first conductors (10) intersecting with parallel spaced-apart second conductors (11). The intersecting first and second conductors define addressable locations where electrons (12) are emitted in response to the application of an energizing voltage. One face of the first conductors is covered with an insulating layer (13) against which the second conductors (11) are applied, this insulating layer (13) forming a tunnel barrier for hot electrons (12) that travel ballistically through and are emitted from the second conductors (11) in response to the application of the energizing voltage. The emitted electrons impinge a target (30, 40, 50) which can be a light-emitting screen of a flat panel display, such as an electroluminescent polymer of a flat panel screen, or an electroluminescent phosphorous screen, or a target wafer bombarded by the electrons emitted from a flexible e-beam lithography mask.

Abstract: This invention relates to a device for emitting addressable locations comprises parallel spaced-apart first conductors (10) intersecting with parallel spaced-apart second conductors (11). The intersecting first and second conductors define addressable locations where electrons (12) are emitted in response to the application of an energizing voltage. One face of the first conductors is covered with an insulating layer (13) against which the second conductors (11) are applied, this insulating layer (13) forming a tunnel barrier for hot electrons (12) that travel ballistically through and are emitted from the second conductors (11) in response to the application of the energizing voltage. The emitted electrons impinge a target (30, 40, 50) which can be a light-emitting screen of a flat panel display, such as an electroluminescent polymer of a flat panel screen, or an electroluminescent phosphorous screen, or a target wafer bombarded by the electrons emitted from a flexible e-beam lithography mask.

Abstract: A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system.