Abstract: At least one example embodiment discloses a semiconductor device including a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, wherein the DMA system includes an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor, a creator configured to create the first data based on the set data transfer parameter, and a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Abstract: At least one example embodiment discloses a semiconductor device including a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, wherein the DMA system includes an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor, a creator configured to create the first data based on the set data transfer parameter, and a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

Abstract: A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.