Patents by Inventor Devesh Dwivedi
Devesh Dwivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230341881Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a LDO regulator circuit and methods of manufacture. The structure includes a comparator connected to a first transistor of a low drop-out (LDO) circuit; a second transistor connected to the first transistor; and a feedback loop connected to the first transistor and an output of the LDO circuit.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Inventors: Siva K. CHINTHU, Suresh PASUPULA, Devesh DWIVEDI, Kevin A. Batson
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Patent number: 11705891Abstract: Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.Type: GrantFiled: May 17, 2022Date of Patent: July 18, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Siva Kumar Chinthu, Devesh Dwivedi, Sundar Veerendranath Palle, Lejan Pu
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Publication number: 20150325286Abstract: Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: International Business Machines CorporationInventors: Devesh Dwivedi, Chandrabhan Kushwah, Sathisha Nanjundegowda
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Patent number: 9177636Abstract: Various embodiments include memory devices and related methods. An embodiment includes circuitry including: a first inverter having a first inverter storage node, the first inverter cross-coupled to a second inverter having a second inverter storage node, wherein each of the first inverter and the second inverter has a reverse bit line controlled feedback transistor coupled between an pull-down transistor and a pull-up transistor, and wherein each pull-down transistor is further coupled to a ground; a first signal line coupled with the reverse bit line controlled feedback transistor of the second inverter; a second signal line coupled with the reverse bit line controlled feedback transistor of the first inverter; a first access transistor coupled with the first inverter storage node, the first signal line, and a third signal line; and a second access transistor coupled with the second inverter storage node, the second signal line, and the third signal line.Type: GrantFiled: May 9, 2014Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Devesh Dwivedi, Chandrabhan Kushwah, Sathisha Nanjundegowda
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Patent number: 8320201Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).Type: GrantFiled: March 30, 2012Date of Patent: November 27, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Amit Kumar Gupta, Devesh Dwivedi, Sanjeev Kumar Jain, Yatender Mishra
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Publication number: 20120188837Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Amit Kumar GUPTA, Devesh DWIVEDI, Sanjeev Kumar JAIN, Yatender MISHRA
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Patent number: 8223572Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.Type: GrantFiled: September 19, 2011Date of Patent: July 17, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Sanjeev Kumar Jain, Devesh Dwivedi
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Publication number: 20120008438Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.Type: ApplicationFiled: September 19, 2011Publication date: January 12, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Sanjeev Kumar JAIN, Devesh Dwivedi
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Patent number: 8040746Abstract: A memory device for efficient word line, bit line and precharge tracking is provided. The memory device includes a memory array, one or more address decoders, a word line driver, a plurality of sense amplifiers, a reference word line column, a reference bit line column, and a control circuit. The control circuit generates a control signal to perform read and write operations on the memory device. The address decoder selects a bit line and a word line. The selected word line is activated by the word line driver. While the reference word line column is used for vertical tracking of the word line, the reference bit line column is used for vertical tracking of the bit line. The sense amplifiers are activated to read the bit line.Type: GrantFiled: June 22, 2009Date of Patent: October 18, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Sanjeev Kumar Jain, Devesh Dwivedi
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Publication number: 20100208538Abstract: A sensing circuit for a semiconductor memory includes a multiplexer coupled to a bit line and a data line coupling the multiplexer to a sense amplifier. The data line is configured to be precharged to a voltage level higher than a precharge voltage level of the bit line.Type: ApplicationFiled: November 17, 2009Publication date: August 19, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Amit Kumar Gupta, Devesh Dwivedi, Sanjeev Kumar Jain, Yatender Mishra
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Publication number: 20100202221Abstract: A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock signal (32) that initiates a read operation. A word line (22) is activated responsive to the triggering edge of the clock signal (32), and data is read from the memory cell (20).Type: ApplicationFiled: November 23, 2009Publication date: August 12, 2010Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Amit Kumar GUPTA, Devesh DWIVEDI, Sanjeev Kumar JAIN, Yatender MISHRA
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Patent number: 7457143Abstract: A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.Type: GrantFiled: April 25, 2006Date of Patent: November 25, 2008Assignee: Infineon Technologies AGInventors: Gunther Lehmann, Siddharth Gupta, Devesh Dwivedi
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Patent number: 7436721Abstract: A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.Type: GrantFiled: September 26, 2006Date of Patent: October 14, 2008Assignee: Infineon Technologies AGInventors: Gunther Lehmann, Yannick Martelloni, Devesh Dwivedi, Siddharth Gupta
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Publication number: 20070247954Abstract: A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.Type: ApplicationFiled: April 25, 2006Publication date: October 25, 2007Applicant: Infineon Technologies AGInventors: Gunther Lehmann, Siddharth Gupta, Devesh Dwivedi
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Patent number: 7242630Abstract: A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.Type: GrantFiled: December 29, 2005Date of Patent: July 10, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Devesh Dwivedi, Ashish Kumar
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Publication number: 20070121400Abstract: A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.Type: ApplicationFiled: September 26, 2006Publication date: May 31, 2007Inventors: Gunther Lehmann, Yannick Martelloni, Devesh Dwivedi, Siddharth Gupta
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Publication number: 20060203536Abstract: A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.Type: ApplicationFiled: December 29, 2005Publication date: September 14, 2006Inventors: Devesh Dwivedi, Ashish Kumar