Patents by Inventor Deyuan Xiao

Deyuan Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10702370
    Abstract: A lumen stent includes a first tube body and a second tube body. The second body is sleeved outside the first body and has at least one end in hermetic connection with the outer surface of the first body. The second body includes a thin film body that covers at least part of the first body and a second radial supporting structure that is disposed in a maximum radius-length region of the thin film body and surrounds the maximum radius-length region. The second radial supporting structure has radius supporting property. After the implantation of the lumen stent, a semi-enclosed gap can be formed between the first body and the second body, or a semi-enclosed gap can be formed between the second body and a tube wall, so that blood flowing into the gap can serve as a filling material and prevent blood from flowing into a tumor body.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 7, 2020
    Assignee: LIFETECH SCIENTIFIC (SHENZHEN) CO., LTD
    Inventors: Chang Shu, Benhao Xiao, Deyuan Zhang
  • Publication number: 20200194315
    Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.
    Type: Application
    Filed: February 25, 2020
    Publication date: June 18, 2020
    Inventor: Deyuan XIAO
  • Patent number: 10624768
    Abstract: A luminal stent includes a first tubular body and a second tubular body sleeved on the first tubular body, and at least one end of the second tubular body is sealingly connected to an outer surface of the first tubular body. In a radial support section of the luminal stent, the first tubular body includes at least one first radial support structure arranged in a circumferential direction thereof, and the second tubular body includes at least one second radial support structure arranged in a circumferential direction thereof and a coating film covering the second radial support structure. The second radial support structure has greater radial deformability than the first radial support structure. After implantation, the luminal stent can form a semi-closed gap between the first tubular body and the second tubular body or between the second tubular body and a lumen wall.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 21, 2020
    Assignee: LIFETECH SCIENTIFIC (SHENZHEN) CO., LTD
    Inventors: Benhao Xiao, Deyuan Zhang, Chang Shu, Yifei Wang
  • Publication number: 20200111785
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel suspended on the subtract, a silicon-deuterium passivation layer on the P-type semiconductor channel; an N-type semiconductor channel suspended on the subtract, a silicon-deuterium passivation layer on the N-type semiconductor channel; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel.
    Type: Application
    Filed: August 29, 2019
    Publication date: April 9, 2020
    Inventor: Deyuan Xiao
  • Patent number: 10615081
    Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: April 7, 2020
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Publication number: 20200105750
    Abstract: The present invention provides a gate-all-around quantum well complementary inverter comprises a first and a second field effect transistor (FET). Channels of the first and second FETs, each of which is surrounded by a gap area, are juxtaposed transversely. A source area and a drain area are positioned at a side of the channel. The channel comprises a semiconductor nano-sheet, a first semiconductor layer fully surrounding semiconductor nano-sheet and a second semiconductor layer fully surrounding the first semiconductor layer. The first semiconductor layer provides a quantum well for holes, and the second semiconductor layer provides a quantum well for electrons. A common gate electrode fully surrounds the gate layer of the first FET and the gate layer of the second FET. The structure of the disclosed device is compact enough to increase the density and improve the performance and simple enough to produce.
    Type: Application
    Filed: August 29, 2019
    Publication date: April 2, 2020
    Inventor: Deyuan Xiao
  • Publication number: 20200105893
    Abstract: The present invention provides a gate-all-around quantum gradient-doped nano-sheet complementary inverter may comprise a P-type field effect transistor (FET) and an N-type FET. The P-type FET may comprise a P-type semiconductor nano-sheet channel, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channel, a first gate layer, and a source and a gate area, arranged at two ends of the channel. The N-type FET may comprise an N-type semiconductor nano-sheet channel, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channel, a second gate layer, and a source and a gate area, arranged at two ends of the channel. A common gate electrode may be arranged to fully surround the first and second gate layers. The doping concentration of the P-type and N-type semiconductor nano-sheet channels, which are arranged laterally, side by side, may be in gradient descent from the surface to the center.
    Type: Application
    Filed: August 28, 2019
    Publication date: April 2, 2020
    Inventor: Deyuan Xiao
  • Publication number: 20200105762
    Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el
    Type: Application
    Filed: August 29, 2019
    Publication date: April 2, 2020
    Inventor: Deyuan Xiao
  • Publication number: 20200075593
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a semiconductor channel, hanging on the subtract; a first semiconductor layer, wrapped all around the semiconductor channel; a second semiconductor layer, wrapped all around the first semiconductor layer; a gate dielectric layer, wrapped all around the second semiconductor layer; and a gate electrode layer, wrapped all around the gate dielectric layer, wherein the first semiconductor layer includes a smaller bandgap than a bandgap of the semiconductor channel. The present inventor includes a quantum well of two dimensional hole gas and a quantum well of two dimensional electron gas, that can improve the electron mobility transistor of holes and electrons, improve the current carrying capacity of N-type Field-Effect Transistor and P-type Field-Effect Transistor, and reduce the resistance and the power consumption.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Inventor: Deyuan Xiao
  • Publication number: 20200075594
    Abstract: This invention provides a semiconductor device and a manufacturing method thereof.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Inventors: Deyuan Xiao, Richard R. Chang
  • Patent number: 10574263
    Abstract: Embodiments of the present application relate to a method for implementing Turbo equalization compensation. The equalizer divides a first data block into n data segments, where D bits in two adjacent data segments in the n data segments overlap, performs recursive processing on each data segment in the n data segments, before the recursive processing, merges the n data segments to obtain a second data block; and performs iterative decoding on the second data block, to output a third data block, where data lengths of the first data block, the second data block, and the third data block are all 1/T of a code length of a LDPC convolutional code.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 25, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Deyuan Chang, Zhiyu Xiao, Fan Yu, Yu Zhao
  • Patent number: 10553496
    Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Zing Semiconductor Corporation
    Inventor: Deyuan Xiao
  • Patent number: 10548709
    Abstract: The present invention provides an aortic arch intraoperative stent, wherein the aortic arch intraoperative stent comprising a main body (17) and one to three branches (5, 6, 7), The aortic arch intraoperative stent connects several circular waveform rings together via a cover membrane (25) to form the main body (17) and the branches (5, 6, 7), wherein each circular waveform ring comprises a circular elastic wire formed through head-to-tail connection. In addition, the present invention also provides a manufacturing method for the aortic arch intraoperative stent, comprising the following steps of: providing a cover membrane mandrel (40); making an inner membrane; assembling circular waveform rings; making an outer membrane; suturing a proximal fabric (12); and suturing a distal fabric (13).
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: February 4, 2020
    Assignee: Lifetech Scientific (Shenzhen) Co. Ltd.
    Inventors: Yongsheng Wang, Zhiyun Xu, Deyuan Zhang, Caiping Liu, Benhao Xiao
  • Patent number: 10523238
    Abstract: The present invention discloses a coding and decoding method, apparatus, and system for forward error correction, and pertains to the field of communications. The method includes: determining check matrix parameters of time-varying periodic LDPC convolutional code according to performance a transmission system, complexity of the transmission system, and a synchronization manner for code word alignment, constructing a QC-LDPC check matrix according to the determined check matrix parameters, and obtaining a check matrix (Hc) of the time-varying periodic LDPC convolutional code according to the QC-LDPC check matrix; de-blocking, according to requirements of the Hc, data to be coded, and coding data of each sub-block according to the Hc, so as to obtain multiple code words of the LDPC convolutional code; and adding the multiple code words of the LDPC convolutional code in a data frame and sending the data frame.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: December 31, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Deyuan Chang, Fan Yu, Zhiyu Xiao
  • Patent number: 10468505
    Abstract: A semiconductor device includes a substrate, a cavity in the substrate, and a germanium (Ge) nanowire suspending in the cavity.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 5, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 10373880
    Abstract: A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Publication number: 20190175327
    Abstract: A luminal stent has a tube body and a skirt surrounding the tube body. The skirt has a flexible connecting section and a stent graft connected to a proximal end of the flexible connecting section. A distal end of the flexible connecting section is sealed and connected to the outer surface of the tube body. A proximal end of the stent graft is suspended and provided with a first radial support structure. When the flexible connecting section is radially compressed, at least a part of the first radial support structure is bent towards a direction distant from the tube body. Also provided is a stent system including the luminal stent. The stent system and the luminal stent can prevent type III endoleaks.
    Type: Application
    Filed: June 28, 2017
    Publication date: June 13, 2019
    Applicant: Lifetech Scientific (Shenzhen) Co., Ltd.
    Inventors: Benhao Xiao, Deyuan Zhang, Chang Shu, Chao Yin, Yifei Wang
  • Patent number: 10170356
    Abstract: This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 1, 2019
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Deyuan Xiao, Richard R. Chang
  • Publication number: 20180330954
    Abstract: A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Inventor: DEYUAN XIAO
  • Patent number: 10100431
    Abstract: This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: October 16, 2018
    Assignee: ZING SEMICONDUCTOR CORPORATION
    Inventors: Deyuan Xiao, Richard R. Chang