Abstract: Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.

Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.

Abstract: According to embodiments of the invention, a system, method and computer program product producing spike-dependent plasticity in an artificial synapse.

Abstract: Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorithm is used to destage a second type of data to the storage for a second duration.

Abstract: A cortical simulator optimizing the simulation scale and time through computationally efficient simulation of neurons in a clock-driven and synapses in an event-driven fashion, memory efficient representation of simulation state, and communication efficient message exchanges.

Abstract: Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.

Abstract: Provided are a method, system and program for using multiple data structures to manage data in cache. A plurality of data structures each have entries identifying data from a first computer readable medium added to a second computer readable medium. A request is received for data in the first computer readable medium. A determination is made as to whether there is an entry for the requested data in one of the data structures. The requested data is retrieved from the first computer readable medium to store in the second computer readable medium in response to determining that there is no entry for the requested data in one of the data structures. One of the data structures is selected in response to determining that there is no entry for the requested data in one of the data structures and an entry for the retrieved data is added to the selected data structure.

Abstract: A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.

Abstract: A method is disclosed for dynamically allocating main memory among applications. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.

Abstract: A cortical simulator optimizing the simulation scale and time through computationally efficient simulation of neurons in a clock-driven and synapses in an event-driven fashion, memory efficient representation of simulation state, and communication efficient message exchanges.

Abstract: A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Abstract: Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorithm is used to destage a second type of data to the storage for a second duration.

Abstract: Provided are a method, system, and article of manufacture for using different algorithms to destage different types of data from cache. A first destaging algorithm is used to destage a first type of data to a storage for a first duration. A second destaging algorithm is used to destage a second type of data to the storage for a second duration.

Abstract: Provided are a method, system, and article of manufacture for managing write requests in cache directed to different storage groups. A determination is made of a high and low thresholds for a plurality of storage groups configured in a storage, wherein the high and low thresholds for one storage group indicate a high and low percentage of a cache that may be used to store write requests to the storage group. A determination is made of a number of tasks to assign to the storage groups based on the determined high and low thresholds for the storage groups, wherein each task assigned to one storage group destages write requests from the cache to the storage group.

Abstract: A self-tuning, low overhead, simple to implements locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Abstract: A storage system has a storage controller for an array of storage disks, the array being ordered in an sequence of write groups. A write cache is shared by the disks. The storage controller temporarily stores write groups in the write cache, responsive to write groups being written, and lists the write groups in order of their sequence in the array and in circular fashion, so that a lowest is listed next to a highest one of the write groups. The storage controller selects the listed write groups in rotating sequence. Such a write group is destaged from the write cache to the disk responsive to i) the selecting of the write group and ii) a state of a recency indicator for the write group, wherein the recency indicator shows recency of writing to the write group.

Abstract: A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Abstract: A cortical simulator optimizing the simulation scale and time through computationally efficient simulation of neurons in a clock-driven and synapses in an event-driven fashion, memory efficient representation of simulation state, and communication efficient message exchanges.

Abstract: A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Abstract: A cortical simulator optimizing the simulation scale and time through computationally efficient simulation of neurons in a clock-driven and synapses in an event-driven fashion, memory efficient representation of simulation state, and communication efficient message exchanges.