Abstract: A structure for for maintaining signal integrity between integrated circuits residing on a printed circuit board. The structure has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Further, the first phase noise is compared with the second phase noise. If the phase noises are about the same, it is determined that the noise source is from an algorithm of a random number generator, the second circuit is modified to optimize the performances of the integrated circuit, and the modified second circuit is copied to the first circuit. If the phase noises are different, it is determined that a source of the phase noise is at least one of a power supply coupling and a substrate coupling in the integrated circuit.

Abstract: A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

Abstract: An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

Abstract: A system and a method for operating the same. The system includes a fractional-N phase-locked loop (PLL). The PLL includes a PLL input and a PLL output. The fractional-N PLL further includes a multiplexer. The multiplexer includes a multiplexer output electrically coupled to the PLL input. The multiplexer further includes M multiplexer inputs, M being an integer greater than 1. Two or more reference frequencies are applied to the inputs of the multiplexer, by the selection of one from the reference frequencies, the low spur can be reached.

Abstract: A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor.

Abstract: A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: An integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Abstract: A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: A light guide device includes a main body having a first incident surface, a second incident surface, an emitting surface, a reflecting surface and a plurality of first microstructures. The first incident surface is opposite to the second incident surface. The emitting surface extends from the first incident surface to the second incident surface. The reflecting surface is opposite to the emitting surface, and the plurality of first microstructures are formed on the reflecting surface and extend parallel to the first and second incident surface. A distribution density and relative size of the first microstructures progressively decrease along directions from a center of the reflecting surface toward the first and second incident surface, respectively. The present light guide device does not employ additional optical correcting elements and thus has a simple structure. A backlight module using the same light guide device is also provided.

Abstract: An exemplary light guide plate (500) includes: a light incident portion (51) for receiving a light; a light reflecting portion (52) for reflecting the light input through the light incident portion; and a light emitting portion (53) opposite to the light reflecting portion, for outputting the reflected light. The light incident portion includes a first diffractive optical element (512) located thereat. The first diffractive optical element includes a plurality of protrusions (512a) each having a curved surface, with the protrusions being arranged symmetrically opposite to each other across a central axis of symmetry of the first diffractive optical element. The light emitting portion may include a second diffractive optical element (532) located thereat. The second diffractive optical element includes a plurality of elongate protrusions, with the protrusions being arranged symmetrically opposite to each other across a central axis of symmetry of the second diffractive optical element.

Abstract: A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

Abstract: A light guide device includes a main body and a plurality of parallel elongate first V-shaped microstructures. The main body has an incident surface; an emitting surface adjoining the incident surface; and a reflecting surface opposite to the emitting surface. The first V-shaped microstructures are provided on the reflecting surface. Each of the first V-shaped microstructures has a triangular cross-section having a first base angle nearest the incident surface, a second base angle furthest from the incident surface and a vertex angle. A pitch between adjacent microstructures is configured to be substantially constant. A size of each of the first V-shaped microstructures is defined by the equation is y=9.2637×10?6x2?0.0003x+0.0232, wherein x is a distance from a given first V-shaped microstructures to the incident surface (in units of micrometers), and wherein y is a base width of the given first V-shaped microstructures (in units of micrometers).

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: An inductor formed on an integrated circuit chip including one or more inner layers between two or more outer layers, inductor metal winding turns included in one or more inner layers, and a magnetic material forming the two or more outer layers and the one or more inner layers. In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips disposed on each of first and second portions of the two or more outer layers and on each of the one or more inner layers. The series of magnetic metallic strips on the first and second portions form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.

Abstract: Wafer-level testing is performed on an electronic device to be used in an optical communications system. An optical test signal is generated and is provided to a first photo detector. An electrical output of the first photo detector is supplied to the electronic device on the wafer. An electrical output from the electronic device on the wafer is used to drive a light source. An optical output of the light source is supplied to a second photo detector and an electrical signal output from the second photo detector is examined.

Abstract: A light guide device (60) and a backlight module using the same. The light guide device includes: an incident surface (61); an emitting surface (64) adjacent to the incident surface; a reflecting surface (62) opposited to the emitting surface; a plurality of first V-shaped structures (644) formed on the emitting surface; and a plurality of second V-shaped structures (622) formed on the reflecting surface and perpendicular to the first V-shaped structures, wherein respective heigths of the second V-shaped structures increase with increasing distance from the incident surface and respective distances between adjacent second V-shaped structures decrease with increasing distance from the incident surface. The light guide device of the present invention does not need optical elements, and thus has a simple structure. A backlight module using the same light guide plate is also provided.

Abstract: A backlight system includes a light guide plate and a light source. The light guide plate includes a light incident surface, a reflective surface adjoining the light incident surface, and a light-emitting surface opposite to the reflective surface. The light guide plate further includes an upper layer and a lower layer under the upper layer. The upper layer includes a substrate portion, a light-emitting surface, a second surface, and a number of projections. The projections extend from the second surface. Each projection has a top extremity adjoining the substrate portion and a bottom face distal from the substrate portion. The lower layer includes a light incident surface, a top surface adjoining the light incident surface, and a reflective surface opposite to the top surface. The top surface of the lower layer abuts the bottom face of the projections.