Patents by Inventor Didem Z. Turker Melek

Didem Z. Turker Melek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10498318
    Abstract: Electrical circuits and associated methods relate to duty cycle correction having a voltage controlled delay line VCDL controlled by an analog voltage and a digital command signal to generate a VCDLout signal. In an illustrative example, the analog voltage may be generated by an analog circuit, the analog circuit may include a reference voltage, a low-pass filter, an amplifier and a loop filter. In an illustrative example, the analog circuit may be controlled by an analog command signal. The analog command signal may be programmable applied on the analog circuit to produce the analog voltage. The digital command signal may be programmable to select desired delay band in the VCDL. The analog voltage and the digital command signal may be applied to the VCDL together to obtain a desired duty cycle.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 3, 2019
    Assignee: XILINX, INC.
    Inventors: Jaewook Shin, Didem Z. Turker Melek, Parag Upadhyaya
  • Patent number: 10348310
    Abstract: An example sigma delta modulator (SDM) circuit includes a floor circuit, a subtractor having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage noise shaping (MASH) converter having a programmable order. The MASH converter includes an input coupled to an output of the subtractor. The SDM further includes a programmable delay circuit having an input coupled to the output of the floor circuit, and an adder having a first input coupled to an output of the MASH converter and a second input coupled to an output of the programmable delay circuit.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Karim M. Megawer, Parag Upadhyaya, Didem Z. Turker Melek, Zhaoyin D. Wu
  • Patent number: 10270450
    Abstract: Methods and apparatus relate to a bidirectional differential interface having a voltage-mode transmit driver architecture formed of multiple selectively enabled slices for coarse output resistance impedance matching. In an illustrative example, the transmit driver may include a programmable resistance for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors, for example, to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors, for example, to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied, for example, through common mode resistors for receive mode operations.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 23, 2019
    Assignee: XILINX, INC.
    Inventors: Shaojun Ma, Parag Upadhyaya, Didem Z. Turker Melek
  • Patent number: 9755600
    Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: September 5, 2017
    Assignee: XILINX, INC.
    Inventors: Didem Z. Turker Melek, Parag Upadhyaya, Kun-Yung Chang
  • Publication number: 20170244371
    Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Applicant: Xilinx, Inc.
    Inventors: Didem Z. Turker Melek, Parag Upadhyaya, Kun-Yung Chang
  • Publication number: 20160322979
    Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Applicant: XILINX, INC.
    Inventors: Parag Upadhyaya, Adebabay M. Bekele, Didem Z. Turker Melek, Zhaoyin D. Wu
  • Patent number: 9237041
    Abstract: A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 12, 2016
    Assignee: XILINX, INC.
    Inventors: Fu-Tai An, Didem Z. Turker Melek, Yuan-Shih Chen
  • Patent number: 8928334
    Abstract: An apparatus relating to on-chip noise measurement is disclosed. In such an apparatus, an asynchronous comparator receives a first input and a second input to provide a digital output. A threshold voltage generator receives a first periodic signal and a second periodic signal to provide the second input as an analog voltage responsive to the first and second periodic signals. A sampling circuit is coupled to receive the digital output signal and a third periodic signal. The sampling circuit is configured to sample the digital output signal using the third periodic signal to provide a sampled signal of the digital output signal. A processor is coupled to receive a delay signal and the sampled signal to determine a noise measurement signal for the first input signal.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 6, 2015
    Assignee: Xilinx, Inc.
    Inventors: Mayank Raj, Didem Z. Turker Melek