Patents by Inventor Didier Dutartre

Didier Dutartre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658578
    Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10?5 ?·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre Morin, Didier Dutartre
  • Patent number: 10535552
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Publication number: 20190267335
    Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.
    Type: Application
    Filed: February 18, 2019
    Publication date: August 29, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventor: Didier DUTARTRE
  • Publication number: 20190244857
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Didier DUTARTRE, Jean-Pierre CARRERE, Jean-Luc HUGUENIN, Clement PRIBAT, Sarah KUSTER
  • Publication number: 20190131520
    Abstract: A memory cell includes a phase-change material. A via is electrically connected with a transistor and an element for heating the phase-change material. An electrically-conductive thermal barrier is positioned between the via and the heating element.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 2, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre MORIN, Franck ARNAUD, Didier DUTARTRE
  • Publication number: 20190131521
    Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10?5 ?·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 2, 2019
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Pierre MORIN, Didier DUTARTRE
  • Patent number: 10263110
    Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Didier Dutartre, Pierre Morin, Francois Andrieu, Elise Baylac
  • Patent number: 10262898
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 16, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Publication number: 20180374983
    Abstract: A method for manufacturing a SPAD photodiode starts with the delimitation of a formation area for the SPAD photodiode in a layer of semiconductor material that is doped with a first dopant type. Dopant of a second dopant type is implanted in the layer of semiconductor material to form a buried region within the formation area. An epitaxial layer is then grown on the layer of semiconductor material at least over the formation area. MOS transistors are then formed on and in the epitaxial layer at locations outside of the formation area.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 27, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Dominique GOLANSKI, Jean JIMENEZ, Didier DUTARTRE, Olivier GONNARD
  • Publication number: 20180166318
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Applicant: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Publication number: 20180096844
    Abstract: A gas phase epitaxial deposition method deposits silicon, germanium, or silicon-germanium on a single-crystal semiconductor surface of a substrate. The substrate is placed in an epitaxy reactor swept by a carrier gas. The substrate temperature is controlled to increase to a first temperature value. Then, for a first time period, at least a first silicon precursor gas and/or a germanium precursor gas introduced. Then, the substrate temperature is decreased to a second temperature value. At the end of the first time period and during the temperature decrease, introduction of the first silicon precursor gas and/or the introduction of a second silicon precursor gas is maintained. The gases preferably have a partial pressure adapted to the formation of a silicon layer having a thickness smaller than 0.5 nm.
    Type: Application
    Filed: May 15, 2017
    Publication date: April 5, 2018
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Victorien Paredes-Saez
  • Patent number: 9929039
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 27, 2018
    Assignee: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Publication number: 20170294379
    Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Didier Dutartre, Jean-Pierre Carrere, Jean-Luc Huguenin, Clement Pribat, Sarah Kuster
  • Publication number: 20170271392
    Abstract: A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Inventor: Didier Dutartre
  • Patent number: 9759546
    Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to th
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 12, 2017
    Assignees: Soitec, STMICROELECTRONICS (Crolles 2) SAS
    Inventors: Oleg Kononchuk, Didier Dutartre
  • Patent number: 9711550
    Abstract: A method of manufacturing a pinned photodiode, including: forming a region of photon conversion into electric charges of a first conductivity type on a substrate of the second conductivity type; coating said region with a layer of a heavily-doped insulator of the second conductivity type; and annealing to ensure a dopant diffusion from the heavily-doped insulator layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 18, 2017
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Laurent Favennec, Didier Dutartre, Francois Roy
  • Patent number: 9704903
    Abstract: A front-side image sensor may include a substrate in a semiconductor material and an active layer in the semiconductor material. The front side image sensor may also include an array of photodiodes formed in the active layer and an insulating layer between the substrate and the active layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 11, 2017
    Assignee: STMICROELECTRONICS SA
    Inventor: Didier Dutartre
  • Publication number: 20170194498
    Abstract: A strained semiconductor layer is produced from a semiconductor layer extending on an insulating layer. A thermal oxidization is performed on the semiconductor layer across its entire thickness to form two bars extending in a direction of a transistor width. Insulating trenches are formed in a direction of a transistor length. A strain of the strained semiconductor layer is induced in one implementation before the thermal oxidation is performed. Alternatively, the strain is induced after the thermal oxidation is performed. The insulating trenches serve to release a component of the strain extending in the direction of transistor width. A component of the strain extending in the direction of transistor length is maintained. The bars and trenches delimit an active area of the transistor include source, drain and channel regions.
    Type: Application
    Filed: December 22, 2016
    Publication date: July 6, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remy Berthelon, Didier Dutartre, Pierre Morin, Francois Andrieu, Elise Baylac
  • Publication number: 20170103913
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Application
    Filed: March 27, 2015
    Publication date: April 13, 2017
    Applicant: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • Publication number: 20160181382
    Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Didier Dutartre, David Barge