Abstract: In accordance with an embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a trip point of a comparator of the ADC by applying a first signal having a first slope to an input of the ADC, and monitoring an output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined trip point of the comparator, monitoring values of an output code of the ADC in response to the second signal, and generating statistical information based on the monitored values of the output code, where the second signal is a static signal or has as second slope less than the first slope.

Abstract: A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.

Abstract: A circuit arrangement includes charge stores logically arranged in an array configuration having logical columns of charge stores including at least first, second, third and fourth columns of charge stores. A control circuit is configured to control a switching network operably coupled to the charge stores, and to affect a first circuit configuration in a first time segment and a second circuit configuration in a second time segment, the circuit configurations being different from one another. In the first circuit configuration, the first and third columns of charge stores receive a first polarity component of a differential signal, and the second and fourth columns of charge stores receive a second polarity component of the differential signal. In the second circuit configuration, the first and second columns of charge stores receive the first polarity component, and the third and fourth columns of charge stores receive the second polarity component.

Abstract: An apparatus for generating a sensor signal indicating information on a capacitance of a variable capacitor including a variable capacitance includes a sensor unit and a compensation unit. The sensor unit is configured to generate a sensor signal indicating information on a varying current flowing through a connection between the sensor unit and the variable capacitor caused by a variation of the capacitance of the variable capacitor while the variable capacitor is biased by a predefined bias voltage. Further, the compensation unit is configured to influence the sensor signal or to provide a compensation signal capable of influencing the sensor signal so that the sensor signal includes less nonlinear signal portions than a sensor signal without the influence of the compensation unit or the compensation signal.

Abstract: Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.

Abstract: This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.

Abstract: In one embodiment, a shunt resistor is provided, comprising two terminals, a semiconductor substrate embodying at least one temperature sensor comprising at least a temperature sensitive element comprising at least one pn-junction, and at least two metal layers above the semiconductor substrate, at least the upper of the metal layer comprising a path that electrically connects the two terminals, whereby the temperature sensor is below and within the periphery of the upper metal layer.

Abstract: This disclosure describes a precise, fast, and relatively low power current-source for use in various applications, which may include driving power semiconductors such power MOSFETs and IGBTs. The current-source may provide both a constant current and a current profile over time which may charge and discharge the steering terminal (e.g. the gate) of a power semiconductor for precise control of switch timing. The current-source uses current steering digital-to-analog converter (DAC) technology and current mirrors to generate a high output current that is significantly immune to power supply and ground variability.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

Abstract: Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

Abstract: Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

Abstract: In one embodiment, a shunt resistor is provided, comprising two terminals, a semiconductor substrate embodying at least one temperature sensor comprising at least a temperature sensitive element comprising at least one pn-junction, and at least two metal layers above the semiconductor substrate, at least the upper of the metal layer comprising a path that electrically connects the two terminals, whereby the temperature sensor is below and within the periphery of the upper metal layer.

Abstract: Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.

Abstract: Methods and devices are provided in which a first parameter partial value (p1) is stored in a first memory (12) and a second parameter partial value (p2) is stored in a second memory (13). A parameter value (p) of a parameter can then be obtained by combining the first parameter partial value (p1) with the second parameter partial value (p2).

Abstract: Apparatuses and methods are described where input signals are supplied to a translinear mesh. In some embodiments an output of the translinear mesh is regulated to a desired value.

Abstract: In one embodiment, a shunt resistor is provided, comprising two terminals, a semiconductor substrate embodying at least one temperature sensor comprising at least a temperature sensitive element comprising at least one pn-junction, and at least two metal layers above the semiconductor substrate, at least the upper of the metal layer comprising a path that electrically connects the two terminals, whereby the temperature sensor is below and within the periphery of the upper metal layer.

Abstract: Representative implementations of devices and techniques provide a linearized high-ohmic resistor. In an example, a quantity of serially connected nonlinear impedances is arranged as a resistance. In one example, the quantity of impedances is applied in an amplifier circuit, between an input of the amplifier and an output of the amplifier, and arranged to set a DC operating point for the amplifier.

Abstract: Multi-channel multiplexers and a method for operating a multi-channel multiplexer are presented, wherein each of a plurality of input channels includes at least one doped bulk well of a conductivity type. The method further includes blocking each input channel of a selection of the plurality of input channels by at least one corresponding control voltage, and bringing each of the at least one doped bulk well of each of the input channels of the selection of the plurality of input channels to an at least one corresponding predetermined voltage. At least one corresponding predetermined voltage is, depending on the conductivity type, either smaller than the corresponding control voltage, or larger than the corresponding control voltage.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.