Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

Abstract: In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1−V2)/2.

Abstract: Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

Abstract: A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

Abstract: An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

Abstract: An electronic driver circuit for word lines in a memory matrix is described. The driver circuit has coded outputs of a driver source, in particular of a current/voltage source, which are switched through to selected word lines. In this context, the word lines are selected in blocks by a control signal, and the outputs of the driver source are connected thereto. The coding of the driver source then selects the respective active word line.

Abstract: An architecture for a magnetoresistive random access memory (MRAM) storage cell 300 with reduced parasitic effects is presented. An additional runs of metal laid in parallel to both the wordline 310 and the bitlines 320 of the MRAM device provide a write wordline 345 and a write bitline 355 are separated from the wordline and the bitline by a dielectric layer 340 and 350 provides electrical isolation of the write currents from the magnetic stacks. The electrical isolation of the write wordline 345 and bitlines 355 reduces the parasitic capacitance, inductance, and resistance seen by the wordline and bitlines during the write operation. The wordline 310 and bitlines 320 remain as in a standard MRAM cross-point array architecture and is dedicated for reading the contents of the MRAM storage cell.

Abstract: A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.

Abstract: The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.

Abstract: A magnetoresitive random access memory (MRAM) configuration is described in which one switching transistor is respectively allocated to a plurality of TMR memory cells. In this manner, the space requirement for constructing the MRAM configuration is greatly reduced because the number of switching transistors required is greatly reduced. Therefore, the packing density of the MRAM configuration can be increased.

Abstract: Unwanted programming by stray magnetic fields is prevented in an MRAM configuration. Compensating currents that counteract the stray magnetic fields are strategically conducted through the MRAM configuration.

Abstract: A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.

Abstract: An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

Abstract: An electronic driver circuit for word lines in a memory matrix is described. The driver circuit has coded outputs of a driver source, in particular of a current/voltage source, which are switched through to selected word lines. In this context, the word lines are selected in blocks by a control signal, and the outputs of the driver source are connected thereto. The coding of the driver source then selects the respective active word line.

Abstract: A magnetoresitive random access memory (MRAM) configuration is described in which one switching transistor is respectively allocated to a plurality of TMR memory cells. In this manner, the space requirement for constructing the MRAM configuration is greatly reduced because the number of switching transistors required is greatly reduced. Therefore, the packing density of the MRAM configuration can be increased.

Abstract: A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.

Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1-V2)/2.