Abstract: In a trellis-coded modulation (TCM) transmission system, data bits are grouped into bit blocks (13), and each such bit block is encoded to select a fixed number w of symbols from a given symbol set (14). The symbols are subdivided into subsets, and each subset includes a few outer symbols and a greater number of inner symbols. Each symbol represents one particular transmission signal value. A first portion (17) of each bit block is separated into w bit subgroups, each of which is separately expanded by a convolutional encoder (20) to obtain a bit combination (19, 15) for specifying one of the symbol subsets. The remaining portion (21) of each bit block is expanded by a block coder (22) to obtain w bit subgroups (23), each being a bit combination (25, 16) for selecting one particular symbol out of a specified subset; outer symbols are selected less frequently than inner symbols.

Abstract: A microprocessor having a single common data bus (17) to which the output (33) of the arithmetic-logic unit (11) as well as input and output of the data memory (13) are connected without intermediate buffer registers. Of the working registers (21, 23, 25, 27) connected to the ALU inputs, one group (21, 23) is loaded from the common data bus and the other group (25, 27), used as accumulators, is directly loaded from the ALU output. Specific control circuitry (51, 53, 55, 57, 59, 61) allows selective storing of ALU output values into accumulators (25, 27), and simultaneous transfer with selective scaling into another register and into an addressed memory location within the same cycle during which the instruction was executed.

Abstract: In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.