Patents by Inventor Dina Triyoso

Dina Triyoso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128308
    Abstract: A method for fabricating a ferroelectric device includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface of the lower electrode layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer on the lower electrode layer using a vapor deposition process. The retention enhancement layer on the lower electrode layer increases the retention performance and reliability of the ferroelectric device.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Inventors: Dina Triyoso, Robert Clark, Kandabara Tapily, Tony Schenk, Alireza Kashir, Stefan Ferdinand Mueller
  • Patent number: 11915973
    Abstract: A substrate processing method includes providing a substrate containing a metal surface and a dielectric material surface, selectively forming a sacrificial capping layer containing a self-assembled monolayer on the metal surface, removing the sacrificial capping layer to restore the metal surface, and processing the restored metal surface and the dielectric material surface. The sacrificial capping layer may be used to prevent metal diffusion into the dielectric material and to prevent oxidation and contamination of the metal surface while waiting for further processing of the substrate.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 27, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Ainhoa Romo Negreira, Yumiko Kawana, Dina Triyoso
  • Patent number: 11894240
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 6, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Patent number: 11882776
    Abstract: Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and encapsulating the MIM stack of an RERAM cell to control the oxygen content in the memory cell dielectric of the RERAM cell. According to one embodiment, a non-oxygen-containing dielectric encapsulation layer is deposited onto the MIM stack in-situ while the substrate remains within the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer within the same processing chamber, the techniques described herein minimize the exposure of the memory cell dielectric to oxygen, while maintaining throughput.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: January 23, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Katie Lutker-Lee, Angelique Raley, Dina Triyoso
  • Publication number: 20220223608
    Abstract: Bilayer stack for a ferroelectric tunnel junction and method of forming. The method includes depositing a first metal oxide film on a substrate by performing a first plurality of cycles of atomic layer deposition, where the first metal oxide film contains hafnium oxide, zirconium oxide, or both hafnium oxide and zirconium oxide, depositing a second metal oxide film on the substrate by performing a second plurality of cycles of atomic layer deposition, where the second metal oxide film contains hafnium oxide and zirconium oxide, and has a different hafnium oxide and zirconium oxide content than the first metal oxide film, and heat-treating the substrate to form a ferroelectric phase in the second metal oxide film but not in the first metal oxide film. A ferroelectric tunnel junction includes a first metal-containing electrode, the first metal oxide film, the second metal oxide film, and a second metal-containing electrode.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventors: Steven Consiglio, Kandabara Tapily, Robert Clark, Dina Triyoso
  • Publication number: 20210313189
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Application
    Filed: February 25, 2021
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Publication number: 20210313513
    Abstract: Methods are provided herein for improving oxygen content control in a Metal-Insulator-Metal (MIM) stack of an RERAM cell, while also maintaining throughput. More specifically, a single chamber solution is provided herein for etching and encapsulating the MIM stack of an RERAM cell to control the oxygen content in the memory cell dielectric of the RERAM cell. According to one embodiment, a non-oxygen-containing dielectric encapsulation layer is deposited onto the MIM stack in-situ while the substrate remains within the processing chamber used to etch the MIM stack. By etching the MIM stack and depositing the encapsulation layer within the same processing chamber, the techniques described herein minimize the exposure of the memory cell dielectric to oxygen, while maintaining throughput.
    Type: Application
    Filed: March 24, 2021
    Publication date: October 7, 2021
    Inventors: Katie Lutker-Lee, Angelique Raley, Dina Triyoso
  • Publication number: 20210175118
    Abstract: A substrate processing method includes providing a substrate containing a metal surface and a dielectric material surface, selectively forming a sacrificial capping layer containing a self-assembled monolayer on the metal surface, removing the sacrificial capping layer to restore the metal surface, and processing the restored metal surface and the dielectric material surface. The sacrificial capping layer may be used to prevent metal diffusion into the dielectric material and to prevent oxidation and contamination of the metal surface while waiting for further processing of the substrate.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 10, 2021
    Inventors: Ainhoa Romo Negreira, Yumiko Kawana, Dina Triyoso
  • Patent number: 10109492
    Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gabriela Dilliway, Dina Triyoso, Elke Erben, Rimoon Agaiby
  • Patent number: 9917016
    Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Klaus Hempel, Dina Triyoso
  • Patent number: 9466661
    Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: October 11, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dina Triyoso, Shao-Fu Sanford Chu, Bo Yu
  • Publication number: 20160172251
    Abstract: Integrated circuits and methods of forming the same are provided. An exemplary method of forming an integrated circuit includes forming a dummy gate structure overlying a semiconductor substrate. The dummy gate structure includes a gate dielectric layer, a dummy gate layer, an etch stop layer, and a dummy gate cap layer. First sidewall spacers are formed adjacent to sidewalls of the dummy gate structure. A source and drain region are formed in the semiconductor substrate adjacent to the first sidewall spacers. A dielectric material is deposited adjacent to the first sidewall spacers. The dummy gate cap layer is etched with a first etchant selective thereto after depositing the dielectric material. The etch stop layer is etched with a second etchant that is selective thereto. The dummy gate layer is etched to form a gate recess, and a gate material is deposited in the gate recess.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Klaus Hempel, Dina Triyoso
  • Publication number: 20160104762
    Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 14, 2016
    Inventors: Dina TRIYOSO, Shao-Fu Sanford CHU, Bo YU
  • Publication number: 20150146341
    Abstract: A thin sub-layer (<15 ?) of an impurity is formed under, over, or inside a thicker layer (˜30-100 ?) of a high-k (k>12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicants: Intermolecular Inc.
    Inventors: Nobumichi Fuchigami, David Paul Brunco, Karthik Ramani, Dina Triyoso
  • Publication number: 20140242788
    Abstract: One illustrative method disclosed herein includes performing an atomic layer deposition (ALD) process at a temperature of less than 400° C. to deposit a layer of silicon dioxide on a germanium-containing region of semiconductor material and forming a gate structure of a transistor device above the layer of silicon dioxide.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Gabriela Dilliway, Dina Triyoso, Elke Erben, Rimoon Agaiby
  • Patent number: 8791003
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 29, 2014
    Assignee: Globalfoundries, Inc.
    Inventors: Dina Triyoso, Elke Erben, Robert Binder
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Publication number: 20130344692
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Dina Triyoso, Elke Erben, Robert Binder
  • Publication number: 20130323923
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Publication number: 20130270656
    Abstract: The present disclosure is generally directed to various replacement gate structures for semiconductor devices. One illustrative gate structure disclosed herein includes, among other things, a gate insulation layer and a layer of gate electrode material with a substantially horizontal portion having a first thickness and a substantially vertical portion having a second thickness that is less than the first thickness. Furthermore, the substantially horizontal portion of the layer of gate electrode material is positioned adjacent to a bottom of the replacement gate structure and above at least a portion of the gate insulation layer, and the substantially vertical portion is positioned adjacent to sidewalls of the replacement gate structure.
    Type: Application
    Filed: January 18, 2013
    Publication date: October 17, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Dina Triyoso, Hao Zhang