Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

Abstract: A memory array including a varying width channel is disclosed. The array includes a plurality of WLs, which are above a layer, where the layer can be, for example, a Select Gate Source (SGS) of the memory array, or an isolation layer to isolate a first deck of the array from a second deck of the array. The channel extends through the plurality of word lines and at least partially through the layer. In an example, the channel comprises a first region and a second region. The first region of the channel has a first width that is at least 1 nm different from a second width of the second region of the channel. In an example, the first region extends through the plurality of word lines, and the second region extends through at least a part of the layer underneath the plurality of word lines. In one case, the first width is at least 1 nm less than a second width of the second region of the channel.

Abstract: Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

Abstract: After reading a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a read voltage for reading operations and then transition a selected wordline of the multiple wordlines from the read voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the read voltage to ground after a delay.

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.

Abstract: A replacement fin in a heterogeneous FinFET transistor in which source and drain regions are grown in corresponding trenches that extend into a sub-fin region. This depth of the epitaxial source/drain regions, in combination with the selected materials, can reduce off-state leakage while also keeping high defect density portions out of the active portions of the source and drain. In one embodiment, materials are selected for the source and drain regions that have an energy band offset from the material selected for the substrate. This band offset between the source/drain material can further reduce sub-fin leakage.

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Abstract: An apparatus is provided which comprises: a source and a drain with a semiconductor body therebetween, the source, the drain, and the semiconductor body on an insulator, a buried structure between the semiconductor body and the insulator, and a source contact coupled with the source and the buried structure, the source contact comprising metal. Other embodiments are also disclosed and claimed.

Abstract: An apparatus is provided which comprises: a source and a drain with a channel region therebetween, the channel region comprising a semiconductor material, and a gate dielectric layer over at least a portion of the channel region, wherein the gate dielectric layer comprises a first thickness proximate to the source and a second thickness proximate to the drain, wherein the second thickness is greater than the first thickness, and wherein at least a portion of the gate dielectric layer comprises a linearly varying thickness over the channel region. Other embodiments are also disclosed and claimed.

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

Abstract: Group III-V semiconductor devices having dual workfunction gate electrodes and their methods of fabrication are described. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. A gate structure is over the channel structure, the gate structure having a first workfunction material laterally adjacent a second workfunction material. The second workfunction material has a different workfunction than the first workfunction material.

Abstract: An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.

Abstract: An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a cap region on the substrate adjacent a second side of the semiconductor region, wherein the cap region comprises semiconductor material of a higher band gap than the semiconductor region, and a drain region comprising doped semiconductor material on the cap region. Other embodiments are also disclosed and claimed.