Patents by Inventor Diwakar Chopperla
Diwakar Chopperla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230297259Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: ApplicationFiled: May 30, 2023Publication date: September 21, 2023Applicant: GOWIN Semiconductor CorporationInventors: Jinghui Zhu, Diwakar Chopperla
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Publication number: 20230205255Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Applicant: GOWIN Semiconductor CorporationInventors: Jianhua Liu, Jinghui Zhu, Ning Song, Tianping Wang, Chienkuang Chen, Diwakar Chopperla, Tianxin Wang, Zhenyu Gu, Xiaozhi Lin
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Patent number: 11662923Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: GrantFiled: July 24, 2020Date of Patent: May 30, 2023Assignee: GOWIN SEMICONDUCTOR CORPORATIONInventors: Jinghui Zhu, Diwakar Chopperla
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Publication number: 20230143302Abstract: A hybrid mode system containing an external device and a field-programmable gate array (“FPGA”) capable of providing configuration data to FPGA via a hybrid communication channel is disclosed. The system is able to identify a first communication protocol in accordance with at least a portion of address bits presented on a serial data line (“SDA”) wherein SDA is used as a connection between FPGA and the external device. The clock signals for receiving data are adjusted to a first clock frequency in accordance with the first communication protocol and clock cycles presented on a serial clock line (“SCL”). SCL is used to connection between FPGA and the external device. After transmitting the configuration data, a portion of FPGA is programmed to perform user-defined logic functions in response to the configuration data.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: GOWIN Semiconductor CorporationInventor: Diwakar Chopperla
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Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
Patent number: 11614770Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.Type: GrantFiled: September 16, 2020Date of Patent: March 28, 2023Assignee: GOWIN SEMICONDUCTOR CORPORATIONInventors: Jianhua Liu, Jinghui Zhu, Ning Song, Tianping Wang, Chienkuang Chen, Diwakar Chopperla, Tianxin Wang, Zhenyu Gu, Xiaozhi Lin -
Publication number: 20230014412Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: GOWIN Semiconductor Corporation, Ltd.Inventors: Jinghui Zhu, Diwakar Chopperla
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Patent number: 11468220Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: GrantFiled: July 24, 2020Date of Patent: October 11, 2022Assignee: GOWIN SEMICONDUCTOR CORPORATIONInventors: Jinghui Zhu, Diwakar Chopperla
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METHODS AND APPARATUS FOR ORGANIZING A PROGRAMMABLE SEMICONDUCTOR DEVICE INTO MULTIPLE CLOCK REGIONS
Publication number: 20220083094Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank 1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.Type: ApplicationFiled: September 16, 2020Publication date: March 17, 2022Applicant: GOWIN Semiconductor CorporationInventors: Jianhua Liu, Jinghui Zhu, Ning Song, Tianping Wang, Chienkuang Chen, Diwakar Chopperla, Tianxin Wang, Zhenyu Gu, Xiaozhi Lin -
Publication number: 20220027071Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: GOWIN Semiconductor CorporationInventors: Jinghui Zhu, Diwakar Chopperla
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Publication number: 20220027543Abstract: A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: GOWIN Semiconductor CorporationInventors: Jinghui Zhu, Diwakar Chopperla
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Patent number: 11216022Abstract: A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.Type: GrantFiled: September 16, 2020Date of Patent: January 4, 2022Assignee: GOWIN Semiconductor CorporationInventors: Jianhua Liu, Jinghui Zhu, Ning Song, Tianping Wang, Chienkuang Chen, Diwakar Chopperla, Tianxin Wang, Zhenyu Gu, Xiaozhi Lin
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Patent number: 11157421Abstract: The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array.Type: GrantFiled: December 29, 2017Date of Patent: October 26, 2021Assignee: GOWIN Semiconductor CorporationInventors: Jinghui Zhu, San-Ta Kow, Tun Jun Gao, Diwakar Chopperla, Chienkuang Chen, Ning Song
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Patent number: 10997088Abstract: A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.Type: GrantFiled: June 26, 2017Date of Patent: May 4, 2021Assignee: GOWIN Semiconductor Corporation, Ltd.Inventors: San-Ta Kow, Jinghui Zhu, Diwakar Chopperla
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Patent number: 10521150Abstract: The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.Type: GrantFiled: July 5, 2018Date of Patent: December 31, 2019Inventors: San-Ta Kow, Jinghui Zhu, Diwakar Chopperla
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Publication number: 20190361624Abstract: The present disclosure provides a data processing method and a device for a nonvolatile memory and a storage medium. The data processing method comprises: performing a full erase operation on the nonvolatile memory if a full erase operation command is received, such that the nonvolatile memory enters an initial state, wherein the initial state refers to a state in which all operations performed on the nonvolatile memory are valid; in the initial state, storing a data if the data is written in the memory is detected, wherein the data comprises a flag information; detecting the flag information if a data readout command triggered by a user is received; and identifying that the nonvolatile memory is in a default state and prohibiting the user from reading the data stored in the nonvolatile memory if the flag information is detected as an unreadable flag information.Type: ApplicationFiled: July 5, 2018Publication date: November 28, 2019Inventors: San-Ta Kow, Jinghui Zhu, Diwakar Chopperla
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Publication number: 20190114268Abstract: The present application discloses a system level integrated circuit chip, comprising a fixed logic module and a Programmable Logic Module; the fixed logic module comprising a CPU module, a non-volatile memory module, a high speed data transmission module, an analogue-to-digital and/or digital-to-analogue conversion module; the Programmable Logic Module comprising a user-defined field programmable gate array and a programmable control module; the CPU module is interconnected with the user-defined field programmable gate array and the programmable control module; the non-volatile memory is interconnected with the user-defined field programmable gate array and the programmable control module; the analogue-to-digital and/or digital-to-analogue conversion module are connected with the user-defined field programmable gate array; and the high speed data transmission module is interconnected with the user-defined field programmable gate array.Type: ApplicationFiled: December 29, 2017Publication date: April 18, 2019Applicant: Gowin Semiconductor CorporationInventors: Jinghui Zhu, San-Ta Kow, Tun Jun Gao, Diwakar Chopperla, Chienkuang Chen, Ning Song
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Publication number: 20180011803Abstract: A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.Type: ApplicationFiled: June 26, 2017Publication date: January 11, 2018Applicant: Gowin Semiconductor Corporation, LtdInventors: San-Ta Kow, Jinghui Zhu, Diwakar Chopperla