Abstract: An Ethernet bridge architecture enables timing replication. The Ethernet bridge receives data packets from a sensor (such as a video sensor) and immediately tags each data packet with a transmitter timecode. The tagged data packets are then forwarded to the appropriate receiver over the digital data network or link that may exhibit packet delivery time variations and reordering. The receiver identifies data packets including the local timecode and delays processing (display) of the data packet until a timecode local to the receiving node matches the transmitter timecode plus some delay. The receiver also restores the original order of the packets by observing packet sequence number and placing them at appropriate location in memory buffer. By delaying processing, the Ethernet bridge compensates for any variance in network latency. The delay should be greater than a worst-case delay as defined by the network architecture.

Abstract: Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.

Abstract: Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.

Abstract: In some aspects, the disclosure is directed to methods and systems for providing voltage regulation and transient suppression from a battery to an integrated circuit. A resistor between a source power supply and the integrated circuit may dissipate power and reduce the voltage at the integrated circuit's input, with current through the resistor under control of an internal regulator of the integrated circuit.

Abstract: In some aspects, the disclosure is directed to methods and systems for providing voltage regulation and transient suppression from a battery to an integrated circuit. A resistor between a source power supply and the integrated circuit may dissipate power and reduce the voltage at the integrated circuit's input, with current through the resistor under control of an internal regulator of the integrated circuit.

Abstract: A network gateway in a vehicle connects heterogeneous networks and buses within the vehicle. The gateway implements hardware acceleration to accomplish protocol translation, e.g., between CAN, LIN, Flexray, and Ethernet buses and networks. In particular, the gateway provides hardware accelerated packet filtering, header lookup, and packet aggregation features.

Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Abstract: A network gateway in a vehicle connects heterogeneous networks and buses within the vehicle. The gateway implements hardware acceleration to accomplish protocol translation, e.g., between CAN, LIN, Flexray, and Ethernet buses and networks. In particular, the gateway provides hardware accelerated packet filtering, header lookup, and packet aggregation features.

Abstract: Efficient architecture for a secure access enforcement proxy is described. The proxy interfaces with multiple subsystems and multiple shared resources. The proxy identifies an original transaction command being sent from one of the subsystems to one of the shared resources, identifies a policy corresponding to the subsystem, performs an action pertaining to the original transaction command based on the policy, and sends a response to the subsystem based on the action.

Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract: Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.

Abstract: Efficient architecture for a secure access enforcement proxy is described. The proxy interfaces with multiple subsystems and multiple shared resources. The proxy identifies an original transaction command being sent from one of the subsystems to one of the shared resources, identifies a policy corresponding to the subsystem, performs an action pertaining to the original transaction command based on the policy, and sends a response to the subsystem based on the action.

Abstract: Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.

Abstract: A device including a two-dimensional convolution unit to perform spatial image filtering. A reference frame mirroring unit is connected to the two-dimensional convolution unit. A mean square error (MSE) decision unit is connected to the two-dimensional convolution unit to perform motion estimation by selecting the displacement that minimizes MSE.

Abstract: Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.

Abstract: One embodiment includes a method that includes receiving a compressed video stream. The method also includes decoding a number of blocks of the compressed video stream to output a number of blocks of decoded video data. The decoding is based on at least one motion compensation vector. The method also includes deinterlacing the number of blocks of the decoded video data to output deinterlaced video data. The deinterlacing of one of the blocks of the number of blocks is based on the at least one motion compensation vector if a prediction error energy for the at least one motion compensation vector for the block is less than a threshold.

Abstract: According to some embodiments, encoded information associated with an image is received at a decoder. The encoded information may be decoded at the decoder to generate full-sized first image pixels representing a full-sized version of the image. Moreover, the full-sized pixels may be scaled at the decoder to generate scaled image pixels representing a scaled version of the image.