Patents by Inventor Dominic Hugo Symes

Dominic Hugo Symes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100332942
    Abstract: A memory controller 4 for a NAND memory array 2 includes error detecting circuitry having input circuitry 6, fast zero-error detecting circuitry 10, fast-path error correcting circuitry 16, 24, slow-path error correcting circuitry 18, 22 and fast-bad-block detecting circuitry 28.
    Type: Application
    Filed: September 10, 2008
    Publication date: December 30, 2010
    Applicant: ARM Limited
    Inventors: Martinus Cornelis Wezelenburg, Thomas Kelshaw Conway, Dominic Hugo Symes
  • Publication number: 20100274990
    Abstract: An apparatus and method for performing SIMD multiply-accumulate operations includes SIMD data processing circuitry responsive to control signals to perform data processing operations in parallel on multiple data elements. Instruction decoder circuitry is coupled to the SIMD data processing circuitry and is responsive to program instructions to generate the required control signals. The instruction decoder circuitry is responsive to a single instruction (referred to herein as a repeating multiply-accumulate instruction) having as input operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicative of a plurality of iterations required, to generate control signals to control the SIMD processing circuitry.
    Type: Application
    Filed: September 17, 2009
    Publication date: October 28, 2010
    Inventors: Mladen Wilder, Dominic Hugo Symes, Richard Edward Bruce
  • Patent number: 7814302
    Abstract: A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: October 12, 2010
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Daniel Kershaw, Mladen Wilder
  • Publication number: 20100217937
    Abstract: A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: ARM LIMITED
    Inventors: Dominic Hugo Symes, Jonathan Sean Callan, Hedley James Francis, Paul Gilbert Meyer
  • Publication number: 20100217958
    Abstract: A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value.
    Type: Application
    Filed: April 30, 2010
    Publication date: August 26, 2010
    Applicant: ARM Limited
    Inventors: Dominic Hugo Symes, Daniel Kershaw, Mladen Wilder
  • Patent number: 7761693
    Abstract: A data processing apparatus includes a register data store that stores data elements, an instruction decoder that decodes an “arithmetic returning high half” instruction, and a data processor that performs data processing operations controlled by the instruction decoder. In response to the decoded arithmetic returning high half instruction, the data processor specifies within the register data store one or more source registers to store a plurality of source data elements of a first size, and one or more destination registers to store a corresponding plurality of resultant data elements of a second size. The second size is half the size of the first size.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: July 20, 2010
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Simon Andrew Ford
  • Patent number: 7747667
    Abstract: A data processing apparatus and method generate an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: June 29, 2010
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Christopher Neal Hinds, Dominic Hugo Symes, Simon Andrew Ford
  • Publication number: 20100122044
    Abstract: A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N-dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two-dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.
    Type: Application
    Filed: July 11, 2006
    Publication date: May 13, 2010
    Inventors: Simon Ford, Dominic Hugo Symes, Alastair Reid
  • Publication number: 20100106944
    Abstract: A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements.
    Type: Application
    Filed: October 14, 2009
    Publication date: April 29, 2010
    Applicant: ARM Limited
    Inventors: Dominic Hugo Symes, Simon Andrew Ford
  • Patent number: 7661104
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 9, 2010
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastian Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Publication number: 20090320048
    Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.
    Type: Application
    Filed: November 17, 2003
    Publication date: December 24, 2009
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Publication number: 20090254736
    Abstract: An apparatus for processing data is provided comprising rearrangement circuitry having a plurality of rearrangement stages for rearranging a plurality N of input data elements, each rearrangement stage comprising at most N multiplexers arranged to select between M data elements where M is in integer less than N. Control circuitry is provided that is responsive to program instructions to control the rearrangement circuitry to perform rearrangement operations. The rearrangement circuitry is configurable by the control circuitry to perform a plurality of different rearrangement operations. The rearrangement circuitry comprises main rearrangement circuitry having a plurality of rearrangement stages in which there is a unique path between any given input element and any given output element and supplementary rearrangement circuitry in which from each input data element there is a path to at most C output data elements where 1<C<N/2.
    Type: Application
    Filed: April 7, 2008
    Publication date: October 8, 2009
    Applicant: ARM Limited
    Inventors: Dominic Hugo Symes, Mladen Wilder
  • Publication number: 20090187746
    Abstract: An apparatus for processing data is provided comprising processing circuitry having permutation circuitry for performing permutation operations, a register bank having a plurality of registers for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to be responsive to a control-generating instruction to generate in dependence upon a bit-mask control signals to configure permutation circuitry for performing permutation operation on an input operand. The bit-mask identifies within the input operand the first group of data elements having a first ordering and a second group of data elements having a second ordering and the permutation operation is such that it preserves one of the first ordering and the second ordering but changes the other of the first ordering and the second ordering.
    Type: Application
    Filed: December 16, 2008
    Publication date: July 23, 2009
    Applicant: ARM LIMITED
    Inventors: Dominic Hugo Symes, Mladen Wilder
  • Publication number: 20090112955
    Abstract: An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further to perform a magnitude-detecting operation. The magnitude-detecting operation calculates a magnitude-indicating result providing an indication of a position of a most-significant bit of a magnitude of a result of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element.
    Type: Application
    Filed: September 5, 2008
    Publication date: April 30, 2009
    Applicant: ARM LIMITED
    Inventors: Daniel Kershaw, Mladen Wilder, Dominic Hugo Symes
  • Patent number: 7448050
    Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 4, 2008
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, Michael Robert Nonweiler, Dominic Hugo Symes
  • Publication number: 20080229073
    Abstract: A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions supported include an address calculation instruction which splits an input address value at a position dependent upon a size value into a first portion and second portion, adds a non-zero offset value to the first portion, sets the second portion to a value and then concatenates the result of the processing on the first portion and the second portion to form the output address value. Another type of instruction supported is a select-and-insert instruction. This instruction takes a first input value and shifts it by N bit positions to form a shifted value, selects N bits from within a second input value in dependence upon the first input value and then concatenates the shifted value with the N bits to form an output value.
    Type: Application
    Filed: February 13, 2008
    Publication date: September 18, 2008
    Applicant: ARM Limited
    Inventors: Dominic Hugo Symes, Daniel Kershaw, Mladen Wilder
  • Patent number: 7426629
    Abstract: A data processing system is provided with mechanisms such that when a data value is stored within a data register, further data values are stored within one or more further registers such that the total number of signal transitions from high to low and from low to high does not vary in dependence upon the data value being written or the previous data value.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: September 16, 2008
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Dominic Hugo Symes, Hedley James Francis
  • Publication number: 20080140750
    Abstract: An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing SIMD processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 12, 2008
    Inventors: Daniel Kershaw, Mladen Wilder, Dominic Hugo Symes
  • Publication number: 20080141004
    Abstract: An apparatus and method are provided for performing re-arrangement operations on data. The data processing apparatus has a register data store with a plurality of registers for storing data, and processing logic for performing a sequence of operations on data including at least one re-arrangement operation. The processing logic has scalar processing logic for performing scalar operations and SIMD processing logic for performing SIMD operations. The SIMD processing logic is responsive to a re-arrangement instruction specifying a family of re-arrangement operations to perform a selected re-arrangement operation from that family on a plurality of data elements constituted by data in one or more registers identified by the re-arrangement instruction. The selected re-arrangement operation is dependent on at least one parameter provided by the scalar processing logic, that parameter identifying a data element width for the data elements on which the selected re-arrangement operation is performed.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 12, 2008
    Applicant: ARM Limited
    Inventors: Daniel Kershaw, Dominic Hugo Symes, Alastair Reid
  • Patent number: 7370210
    Abstract: The present invention provides a data processing apparatus and method for managing processor configuration data. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain, at least one secure mode being a mode in the secure domain, and a monitor mode. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when said processor is operating in a non-secure mode.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: May 6, 2008
    Assignee: Arm Limited
    Inventor: Dominic Hugo Symes