Patents by Inventor Dominic Maier

Dominic Maier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8990744
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Brückl, Rainer Leuschner
  • Publication number: 20150064846
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20150041967
    Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Infineon Technologies AG
    Inventors: Ulrich Wachter, Veronika Huber, Thomas Kilger, Ralf Otremba, Bernd Stadler, Dominic Maier, Klaus Schiess, Andreas Schlögl, Uwe Wahl
  • Publication number: 20150028435
    Abstract: A method of packaging integrated circuits includes providing a molded substrate that has a plurality of first semiconductor dies and a plurality of second semiconductor dies laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the second semiconductor dies. The exposed second semiconductor dies are removed to form cavities in the molded substrate. A plurality of third semiconductor dies are inserted in the cavities formed in the molded substrate, and electrical connections are formed to the first semiconductor dies and to the third semiconductor dies.
    Type: Application
    Filed: August 7, 2014
    Publication date: January 29, 2015
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Patent number: 8890284
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Publication number: 20140332936
    Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 13, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Dominic Maier, Ulrich Wachter, Daniel Kehrer
  • Publication number: 20140310671
    Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Inventors: Gottfried Beer, Dominic Maier, Gerhard Metzger-Brückl, Rainer Leuschner
  • Patent number: 8828807
    Abstract: A method of packaging integrated circuits includes providing a molded substrate including a first plurality of functional semiconductor dies and a plurality of placeholders laterally spaced apart from one another and covered by a molding compound. The molding compound is thinned to expose at least some of the placeholders. The exposed placeholders are removed to form cavities in the molded substrate. A second plurality of functional semiconductor dies is inserted in the cavities formed in the molded substrate. Electrical connections are formed to the first plurality and second plurality of functional semiconductor dies at a side of the dies uncovered by the molding compound.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
  • Publication number: 20140239438
    Abstract: A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices.
    Type: Application
    Filed: February 22, 2013
    Publication date: August 28, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kilger, Ulrich Wachter, Dominic Maier, Gottfried Beer
  • Patent number: 8421226
    Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: April 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Ludwig Heitzer, Dominic Maier
  • Publication number: 20110204513
    Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.
    Type: Application
    Filed: February 25, 2010
    Publication date: August 25, 2011
    Inventors: Thorsten Meyer, Ludwig Heitzer, Dominic Maier