Abstract: An electronic circuit has an amplifier with an amplifying transistor and a cascode transistor. A capacitive voltage divider applies a fraction of an RF signal swing from the drain of the cascode transistor to the gate of the cascode transistor, the fraction being determined by a ratio between capacitance values. In addition a bias voltage supply circuit is provided. The bias voltage supply circuit is configured to define a relation between an average gate voltage of the cascode transistor and an average drain supply voltage at the drain of the cascode transistor. This relation increases the average gate voltage with increasing average drain voltage, and the relation provides a non zero average gate voltage when extrapolated to zero average drain supply voltage.

Abstract: An electronic circuit has an amplifier with an amplifying transistor (260) and a cascode transistor (262). A capacitive voltage divider (268) applies a fraction of an RF signal swing from the drain of the cascode transistor (262) to the gate of the cascode transistor (262), the fraction being determined by a ratio between capacitance values. In addition a bias voltage supply circuit (29, 290, 266) is provided. The bias voltage supply circuit is configured to define a relation between an average gate voltage of the cascode transistor (262) and an average drain supply voltage at the drain of the cascode transistor (262). This relation increases the average gate voltage with increasing average drain voltage, and the relation provides a non zero average gate voltage when extrapolated to zero average drain supply voltage.

Abstract: The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL1) frequency by an odd integer. A digital value is shifted into a set of latches based on the clock signal (CL1) and kept there a predetermined number of half clock cycles. The value is shifted into a following latch delayed with half a clock cycle of the clock signal compared with a previous latch. Then a first (Q1) and a second (Q6) intermediate signal, each provided through information stored in a latch, are interpolated for forming said first output signal (O Q). Because of this it is possible to provide an output signal having edges displaced from clock signal edges, thus allowing a higher resolution than the original clock signal has and in particular, enabling quadrature outputs from a standard odd-integer frequency divider.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (C1, NC0; C2, NC2; C3, NC3) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs (Ip, In, Qp, Qn; INi, INni, INq, Innq) according to the control signals (C0, NC0; C1, NC1; C2, NC2). Said phase selection unit (PSU) is implemented based on direct logic.

Abstract: A transmitter comprises a power amplifier (PA) which has an amplifier powersupply input (PI) and an output (PAO) to supply a transmission signal (Vo) with an output power (Po). A power supply (PS) has power supply outputs (PSO1, PSO2) to supply a first power supply voltage (PV1) and a second power supply voltage (PV2). A switching circuit(SC) is arranged between the power supply outputs (PSO1, PSO2) and the amplifier powersupply input (PI).

Abstract: The invention relates to a planar inductive component arranged over a substrate (103). The substrate in a first plane, a patterned ground shield (102), for shielding the winding (101) from the substrate (103). The winding (101) is at least substantially symmetrical plane. The patterned ground shield (102) comprises a plurality of electrical conductive first tracks (105) situated in a first ground shield plane in parallel with the first plane. The first tracks have an orientation perpendicular to the mirror plane (104). Without the patterned ground shield (102) the winding (101) is capacitively coupled to the substrate (103). The substrate resistance results in a degradation of the quality factor of the inductive component (100). The patterned ground shield (102) shields the winding (101) from the substrate (103), thereby eliminating the degrading effect of the substrate.

Abstract: A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).

Abstract: Telecommunication systems comprising transmitting units (1) and receiving units (11), with units (1 resp. 11) comprising parallel chains (2-4 resp. 12-14) coupled to processing parts (5 resp. 15), have enhanced data rates/channel capacities, under the assumption that the noise in the chains (2-4 resp. 12-14) is uncorrelated. Correlated noise from external noise sources decreases said rates/capacities. By coupling said chains (2-4 resp. 12-14) to said processing parts (5 resp. 15) via switches (6 resp. 16) for uncorrelating correlated noise in said chains (2-4 resp. 12-14), any correlated noise present in chains (2-4 resp. 12-14) is made uncorrelated. Said switch (30,50,70) (over/sub)samples chain signals, and is further coupled to said processing part (32,52,72) for controlling purposes to switch randomly or programmedly, with said processing part (32,52,72) and said switch (30,50,70) operating synchronically.

Abstract: A differential amplifier for amplifying an input differential signal having two components (In+, In?) substantially in anti-phase to each other and generating an output differential signal having two differential components (Out+, Out?). The amplifier comprises a pair of inverters coupled to a pair of adders the inverters receiving the input differential signal. The amplifier is characterized in that it further comprises a pair of controllable buffers for receiving the input differential signal and outputting a signal to the pair of adders. A bias of the said pair of buffers is cross-controlled by the input differential signal for controlling an amplification of said pair of controllable buffers.

Abstract: In a method of the invention for providing clock signals to a mixed signal telecommunication chip having a communication signal in a communication signal band, said clock signals comprise a central clock frequency signal and sub-frequency signals which are multiples or divisions of said central clock frequency signal. The central clock frequency signal is selected such that the central clock frequency signal and the sub-frequency signals are located outside the telecommunication signal band. The a mixed signal telecommunication chip of the invention takes advantage of the above clock planning.