Patents by Inventor Dominique Delbecq

Dominique Delbecq has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10496471
    Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 3, 2019
    Assignee: NXP USA, Inc.
    Inventors: Andres Barrilado Gonzalez, Ralf Reuter, Dominique Delbecq, Francesco d'Esposito, Arnaud Sion, Gustavo Adolfo Guarin Aristizabal, Marcel Christoph Welpot
  • Patent number: 10211840
    Abstract: A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pierre Pascal Savary, Dominique Delbecq, Birama Goumballa
  • Patent number: 10120064
    Abstract: The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: November 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Cristian Pavao-Moriera, Dominique Delbecq, Birama Goumballa
  • Publication number: 20180292511
    Abstract: A radar device (100) is described that includes at least one transceiver (205) configured to support frequency modulated continuous wave (FMCW); a digital controller (262); and a temperature sensor system comprising a plurality of temperature sensors (222, 232, 242) coupled to various circuits (220, 230, 240) in the at least one transceiver (205). The digital controller (262) of the radar device (100) is configured to monitor a temperature of the various circuits (220, 230, 240) by polling temperature values of the plurality of temperature sensors (222, 232, 242).
    Type: Application
    Filed: March 9, 2018
    Publication date: October 11, 2018
    Inventors: Matthis Bouchayer, Cristian Pavao Moreira, Dominique Delbecq, Pierre Savary
  • Patent number: 10033367
    Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: July 24, 2018
    Assignee: NXP USA, Inc.
    Inventors: Cristian Pavao-Moreira, Dominique Delbecq, Birama Goumballa, Didier Salle
  • Patent number: 10006987
    Abstract: A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: June 26, 2018
    Assignee: NXP USA, Inc.
    Inventors: Cristian Pavao-Moreira, Dominique Delbecq, Birama Goumballa
  • Patent number: 9973360
    Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 15, 2018
    Assignee: NXP USA, Inc.
    Inventors: Olivier Vincent Doare, Dominique Delbecq, Gilles Montoriol
  • Publication number: 20180121282
    Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.
    Type: Application
    Filed: September 15, 2017
    Publication date: May 3, 2018
    Inventors: Andres Barrilado Gonzalez, Ralf Reuter, Dominique Delbecq, Francesco d'Esposito, Arnaud Sion, Gustavo Adolfo Guarin Aristizabal, Marcel Christoph Welpot
  • Publication number: 20180013436
    Abstract: A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    Type: Application
    Filed: January 20, 2017
    Publication date: January 11, 2018
    Inventors: Pierre Pascal Savary, Dominique Delbecq, Birama Goumballa
  • Patent number: 9835715
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesizer, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: December 5, 2017
    Assignee: NXP USA, Inc.
    Inventors: Dominique Delbecq, Olivier Doare, Gilles Montoriol
  • Publication number: 20170180169
    Abstract: A phase shifter controller arranged to generate phase shift control signals for at least one phase shifter. The phase shifter controller is arranged to receive a first phase value ?1, receive a second phase value ?2, and output phase shift control signals. The phase shifter controller comprises a digital synthesizer arranged to compute a first digital phase shift control value based on the received first phase value ?1, and compute a second digital phase shift control value based on the received second phase value ?2. The phase shifter controller further comprises digital to analogue converters arranged to generate the phase shift control signals based on the derived first and second digital phase shift control values.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 22, 2017
    Inventors: Olivier Vincent Doare, Dominique Delbecq, Gilles Montoriol
  • Publication number: 20160266239
    Abstract: The embodiments described herein provide a radar device and method that can provide improved sensitivity. In general, the embodiments described herein provide a saturation detector and reset mechanism coupled to a radar receiver. The saturation detector is configured to detect saturation events in the radar receiver, and the reset mechanism is configured to reset at least one filter unit in the radar receiver in response to detected saturation events. As such, the embodiments can facilitate improved radar sensitivity by reducing the effects of saturation events in the radar receiver.
    Type: Application
    Filed: August 19, 2015
    Publication date: September 15, 2016
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA
  • Patent number: 9438358
    Abstract: A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. The multiplexer unit may be connected to the mixer and to the test signal unit and arranged to select, among the reception signal and a test signal, a multiplexer output signal in dependence on an operating signal. The amplifier unit may be connected to the multiplexer unit and arranged to amplify the multiplexer output signal, thereby generating an amplified signal. The signal strength unit may be connected to the amplifier unit and arranged to generate a signal strength indicator indicative of a signal strength of the amplified signal.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominique Delbecq, Fares Jaoude
  • Patent number: 9379721
    Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: June 28, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cristian Pavao-Moreira, Dominique Delbecq, Jean-Stephane Vigier
  • Publication number: 20160154092
    Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.
    Type: Application
    Filed: May 4, 2015
    Publication date: June 2, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA, DIDIER SALLE
  • Publication number: 20160109559
    Abstract: An integrated circuit for a radar device comprises at least one transmitter and at least one receiver. The integrated circuit comprises: a direct digital synthesiser, DDS, configured to output a control signal; and a multiplier configured to receive a local oscillator input signal and a further input signal from the DDS. In a first mode of operation, the DDS and multiplier cooperate to generate at least one transmitter signal to be transmitted from the radar device; and in a second mode of operation the DDS and multiplier cooperate to generate at least one low frequency modulated transmitter signal to be internally routed to the at least one receiver for calibrating the at least one receiver.
    Type: Application
    Filed: March 17, 2015
    Publication date: April 21, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: DOMINIQUE DELBECQ, OLIVIER DOARE, GILLES MONTORIOL
  • Publication number: 20160103206
    Abstract: A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.
    Type: Application
    Filed: March 9, 2015
    Publication date: April 14, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: CRISTIAN PAVAO-MOREIRA, DOMINIQUE DELBECQ, BIRAMA GOUMBALLA
  • Patent number: 9306619
    Abstract: A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: April 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert Gach, Dominique Delbecq
  • Patent number: 9197403
    Abstract: An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Laurent Gauthier, Dominique Delbecq, Jean-Stephane Vigier
  • Publication number: 20150326235
    Abstract: An electronic device has a capacitive arrangement for controlling a frequency characteristic. The capacitive arrangement has varactor banks having a number of parallel coupled varactors and a control input for switching the respective varactors on or off. A main varactor bank has N varactors and a series varactor bank has A varactors, the main varactor bank being connected in series with the series varactor bank. A shunt varactor bank of B varactors may be coupled to a ground reference and connected between the main varactor bank and the series varactor bank. When a varactor is switched in the main varactor bank, it provides an equivalent capacitance step size (or frequency step) smaller than size of a capacitance step when switching a single varactor on or off. According to the number of varactors selected in the shunt varactor, B, this frequency step can be made programmable.
    Type: Application
    Filed: July 6, 2012
    Publication date: November 12, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Cristian PAVAO-MOREIRA, Dominique DELBECQ, Jean St├ęphane VIGIER