Patents by Inventor Don-Hyun Choi
Don-Hyun Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240079078Abstract: A semiconductor device includes a redundancy control signal generation circuit configured to generate a redundancy control signal by determining whether a row address for an active operation has been repaired through a soft post package repair operation and determining whether a row hammer phenomenon has occurred with respect to the row address. The semiconductor device also includes a first selection address generation circuit configured to generate a first selection address for driving a sub word line or a redundancy word line from one of a repair address and a first internal address, based on the redundancy control signal. The semiconductor device further includes a second selection address generation circuit configured to generate a second selection address for driving the sub word line or the redundancy word line from one of a fixed address and a second internal address, based on the redundancy control signal.Type: ApplicationFiled: December 27, 2022Publication date: March 7, 2024Applicant: SK hynix Inc.Inventors: Sang Hyun KU, Don Hyun CHOI
-
Patent number: 10607684Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.Type: GrantFiled: December 6, 2018Date of Patent: March 31, 2020Assignee: SK hynix Inc.Inventors: Seung Min Yang, Kyoung Youn Lee, Byeong Cheol Lee, Don Hyun Choi
-
Publication number: 20200013450Abstract: A semiconductor device includes a delay time adjustment circuit and an address input circuit. The delay time adjustment circuit adjusts a point in time when charges are supplied to internal nodes according to a voltage level of a back-bias voltage in response to a test mode signal. The delay time adjustment circuit also delays an active signal by a first delay time varying according to amounts of charge of the internal nodes to generate a bank selection signal. The address input circuit is driven by the back-bias voltage. The address input circuit receives an address in response to the bank selection signal to generate an internal address. The address input circuit delays the address by a second delay time varying according to a voltage level of the back-bias voltage.Type: ApplicationFiled: December 6, 2018Publication date: January 9, 2020Applicant: SK hynix Inc.Inventors: Seung Min YANG, Kyoung Youn LEE, Byeong Cheol LEE, Don Hyun CHOI
-
Patent number: 9595351Abstract: A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals. The sub word line driver group is configured so that inactivated sub word line drivers are arranged between activated sub word line drivers while the decoding unit is operating in the test mode.Type: GrantFiled: October 14, 2015Date of Patent: March 14, 2017Assignee: SK hynix Inc.Inventor: Don Hyun Choi
-
Publication number: 20170053715Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.Type: ApplicationFiled: November 5, 2015Publication date: February 23, 2017Inventors: Jae Il KIM, Seung Geun BAEK, Don Hyun CHOI
-
Patent number: 9576684Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.Type: GrantFiled: November 5, 2015Date of Patent: February 21, 2017Assignee: SK HYNIX INC.Inventors: Jae Il Kim, Seung Geun Baek, Don Hyun Choi
-
Publication number: 20160329108Abstract: A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals. The sub word line driver group is configured so that inactivated sub word line drivers are arranged between activated sub word line drivers while the decoding unit is operating in the test mode.Type: ApplicationFiled: October 14, 2015Publication date: November 10, 2016Inventor: Don Hyun CHOI
-
Patent number: 9455008Abstract: A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.Type: GrantFiled: May 15, 2014Date of Patent: September 27, 2016Assignee: SK hynix Inc.Inventor: Don Hyun Choi
-
Publication number: 20150235687Abstract: A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.Type: ApplicationFiled: May 15, 2014Publication date: August 20, 2015Applicant: SK hynix Inc.Inventor: Don Hyun CHOI
-
Patent number: 8810295Abstract: A latch circuit may include a first inverting unit configured to drive a second node in response to a level of a first node, a second inverting unit configured to drive the first node in response to a level of the second node, an initialization unit configured to drive the first node at a first level in response to activation of an initialization signal, and a power breaker configured to break a supply of power of a second level to the second inverting unit when the initialization signal is activated.Type: GrantFiled: December 17, 2012Date of Patent: August 19, 2014Assignee: SK Hynix Inc.Inventors: Ja-Beom Koo, Kang-Youl Lee, Don-Hyun Choi
-
Patent number: 8750063Abstract: A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a precharge voltage to the plurality of BLSAs in response to a control signal.Type: GrantFiled: September 3, 2012Date of Patent: June 10, 2014Assignee: SK Hynix Inc.Inventor: Don Hyun Choi
-
Publication number: 20130315017Abstract: A sense amplifier control circuit according to the present invention is disposed in a bit line sense amplifier (BLSA) array region including a plurality of BLSAs and is configured to supply a precharge voltage to the plurality of BLSAs in response to a control signal.Type: ApplicationFiled: September 3, 2012Publication date: November 28, 2013Applicant: SK hYNIX Inc.Inventor: Don Hyun CHOI
-
Publication number: 20130307595Abstract: A latch circuit may include a first inverting unit configured to drive a second node in response to a level of a first node, a second inverting unit configured to drive the first node in response to a level of the second node, an initialization unit configured to drive the first node at a first level in response to activation of an initialization signal, and a power breaker configured to break a supply of power of a second level to the second inverting unit when the initialization signal is activated.Type: ApplicationFiled: December 17, 2012Publication date: November 21, 2013Applicant: SK HYNIX INC.Inventors: Ja-Beom KOO, Kang-Youl LEE, Don-Hyun CHOI
-
Patent number: 7952954Abstract: A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test mode signal.Type: GrantFiled: December 30, 2008Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Don-Hyun Choi
-
Publication number: 20090316504Abstract: A semiconductor integrated circuit includes a row main signal generation section configured to provide a row main signal serving as a driving reference for a plurality of row-series circuit units in response to a bank active signal, wherein activation timing of the row main signal is controlled by a test mode signal.Type: ApplicationFiled: December 30, 2008Publication date: December 24, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Don Hyun Choi