Abstract: A high speed data transfer method and apparatus. A high speed data bus includes separate data transfer and master control bus portions. A system host computer loads a sequence of source and destination addresses corresponding to communications units coupled to the bus into memory in a bus master controller. The bus controller sequences through these address pairs at an aggregate rate greater than at least some of the devices' ability to transfer data to enhance data transmission speed on the bus. Bus cycles are allocated to devices on the bus according to a scheme dependent on those devices ability to utilize the bus. High speed devices are allocated a greater number of bus cycles per unit time than slower devices.