Abstract: A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program.

Abstract: A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program.

Abstract: A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program.

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Abstract: A diffused MOS (DMOS) device and method for making same are disclosed. The prior art DMOS device is improved upon by ion implanting a depletion extension L.sub.D to the drain. However, the introduction of the depletion extension L.sub.D introduces a manufacturing statistical variation in the characteristics of the resultant devices so produced. The problem of the effects of the variations in the length L.sub.D and thus, variations in the resulting transconductance of the device, is solved by placing two of these devices in parallel. When one device has its L.sub.D relatively shorter, the companion device will also have its L.sub.D correspondingly longer. The method of producing the dual devices is by ion implanting a single conductivity region which forms the L.sub.D for both the left- and right-hand channels for the left- and right-hand DMOS structures. If the mask for the ion-implanted region is misaligned slightly to the right, then the effective L.sub.

Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure.

Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure.

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A thin n-type region is implanted in a portion of the p-type channel region of an FET device adjacent to the drain diffusion. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A thin n-type region is implanted in a portion of the p-type channel region of an FET device adjacent to the drain diffusion. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.