Patents by Inventor Donald E. Lewis

Donald E. Lewis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10343634
    Abstract: An apparatus includes a vehicle structure, a bumper, an elongate structural member, and an extension portion. The elongate structural member is able to crush longitudinally in response to application of force in a longitudinal direction. The extension portion is able to crush longitudinally in response to application of force in the longitudinal direction, is connected to the elongate structural member such that the elongate structural member and the extension portion support the bumper with respect to the vehicle structure, and is operable to move the bumper between an extended position and a retracted position with respect to the vehicle structure to change a distance between the bumper and the vehicle structure.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 9, 2019
    Assignee: Apple Inc.
    Inventors: Erik Mikael Fermer, Alice C. Watts, Joel Frederic Jensen, Ronald Jack Smith, Mark B. Rober, Sung Hoon Kim, David Jennings Dostal, Russell Cranstoun Mead, Jr., Todd Elliot Lewis, Jesse T. Buehler, Nathaniel J. Dennis, Tommaso P. Rivellini, Robert R. Mayer, Anthony S. Montevirgen, Donald J. Parr, Bryce A. Woollard, Adam J. Golman, Kevin P. Makowski, Daniel E. Rivera
  • Patent number: 8890739
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8890729
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: January 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152478
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: January 26, 2013
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Publication number: 20140152477
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Application
    Filed: December 5, 2012
    Publication date: June 5, 2014
    Applicant: CREST SEMICONDUCTORS, INC.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
  • Patent number: 8525556
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: September 3, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Patent number: 8497790
    Abstract: A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: July 30, 2013
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Paul Talmage Watkins, Rex K. Hales, Yusuf Haque
  • Publication number: 20120194223
    Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: SIFLARE, INC.
    Inventors: Ramesh Kumar Singh, Yusuf Haque, Donald E. Lewis
  • Patent number: 7898452
    Abstract: This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: March 1, 2011
    Assignee: Siflare, Inc.
    Inventors: Donald E. Lewis, Rex K. Hales
  • Patent number: 7688238
    Abstract: A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: March 30, 2010
    Assignee: Slicex, Inc.
    Inventors: Donald E. Lewis, Rex K. Hales
  • Publication number: 20100066575
    Abstract: This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Applicant: SLICEX, INC.
    Inventors: Donald E. Lewis, Rex K. Hales
  • Publication number: 20080238740
    Abstract: A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 2, 2008
    Inventors: Donald E. Lewis, Rex K. Hales
  • Patent number: 7302823
    Abstract: A pipe bending system employing a sensing and indicating system that provides feedback to an operator regarding the position of components of the pipe bending system, such as the pin-up shoe and the stiffback. Apparatus for retrofitting a sensing and indicating system to existing pipe bending apparatus.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: December 4, 2007
    Assignee: CRC-Evans Pipeline International, Inc.
    Inventors: Jimmie D. Jackson, Donald E. Lewis
  • Patent number: 6253595
    Abstract: A pipe bending system employing a feedback and control system that provides continuous data to a programmed processor. The processor is programmed to automatically carry out an incremental bending cycle in which the pipe is clamped by a predefined pressure by the pin-up shoe, a stiffback is moved upwardly to a predefined position to achieve a desired angular bend in the pipe, the stiffback is returned to its fill back position, as is the pin-up shoe, whereupon the pipe is axially moved a predefined distance to proceed with the subsequent incremental bend.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: July 3, 2001
    Assignee: CRC-Evans Pipeline International, Inc.
    Inventor: Donald E. Lewis, Jr.
  • Patent number: 6115624
    Abstract: An intrauterine catheter device for monitoring fetal and/or maternal heart rate, including an elongate housing having proximal and distal portions, an array of ECG electrodes on the distal portion and one or more acoustic or other mechanical sensors on the distal portion. A pressure transducer may also be provided on the distal portion. Processor circuitry compares the ECG signal with the output signal of the acoustic sensor to derive fetal and/or maternal heart rate. An intrauterine catheter device is also provided, including a reference electrode on its distal portion, and an array of active electrodes spaced apart from one another on the distal portion. The device may also include a pressure transducer on the distal portion and processor circuitry coupled to the array of active electrodes and/or to the reference electrode for deriving fetal ECG from signals produced by the array of active electrodes.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: September 5, 2000
    Assignee: Genesis Technologies, Inc.
    Inventors: Donald E. Lewis, George D. Park, Randall I. Park
  • Patent number: 5139482
    Abstract: An apparatus for signalling an accidental loss of blood from a patient's fluid infusion line includes a sensor assembly for connection to the line, the assembly having a housing for receiving a portion of the line within a side opening, a holder having a clamp member for drawing together portions of the housing on opposite sides of the side opening for fixing the portion of the line within the opening relative to the housing, a source of radiation directed through the opening for intersecting the line, and a radiation detector in the housing for receiving radiation that is transmitted from the source through the line. The apparatus further includes a battery powered circuit, the circuit intermittently powering the radiation source, and producing a reference voltage, a train of signal pulses forming a sensor signal that is indicative of the radiation received by the detector and, when the sensor signal is in a predetermined relationship with the reference signal, an alarm signal.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: August 18, 1992
    Inventors: Paula S. Simeon, Donald E. Lewis
  • Patent number: 5052215
    Abstract: A system and method for injecting gas or fluid in the base beneath an above ground storage tank to enhance the rate of any leakage in the bottom of the tank, and detecting and locating the leak by acoustic sensors placed about the tank. The leak may then be sealed by injecting sealant through a probe placed beneath the tank in the area of the leak.
    Type: Grant
    Filed: October 18, 1990
    Date of Patent: October 1, 1991
    Inventor: Donald E. Lewis
  • Patent number: 4896528
    Abstract: Method and apparatus are described for detecting the leakage of fluid under storage tanks. A number of parallel perforated test conduits are placed under the tank which is to be tested for leaks. A vacuum is placed on the test conduits to remove gas and liquid, if any, from the soil beneath the tank. If no gas or liquid is found it indicates that there is no leak. If gas or liquid is found, small test areas are isolated under the tank. The isolated areas may be placed under vacuum or pressure so gas and/or liquid can flow therethrough under pressure so that analysis of the flow in or flow out of the test conduit can be made to determine if that isolated area has leakage. The isolated areas can be changed until the isolated area with the leak is found.
    Type: Grant
    Filed: November 16, 1987
    Date of Patent: January 30, 1990
    Inventor: Donald E. Lewis
  • Patent number: 4556222
    Abstract: A typical fluid mixer of the heavy-duty type conventionally has a compartment including walls, one of which has a circular opening through which a motor-driven shaft extends. An external seal is provided for sealing the shaft-to-wall junction against fluid leakage. When it becomes necessary to replace the seal, the compartment must be drained to avoid leakage at the opening. The present invention provides an internal seal that is normally spaced along the shaft away from the wall but which can be forcibly moved toward and compressed against the wall and thus seal the shaft and opening and preventing leakage during repairs and consequently eliminating emptying the tank. The interior seal is supported by a movable carrier, and reversible force-exerting mechanism extending exteriorly of the compartment is employed to move the carrier and interior seal into and out of its interior sealing position. In a preferred embodiment, the force-exerting mechanism includes one or more jack screws.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: December 3, 1985
    Inventors: Donald E. Lewis, Delmar D. Lewis
  • Patent number: 4377824
    Abstract: An apparatus and method for recording and reproducing extended periods of video information on a longitudinal tape recorder without losing synchronism or image quality. The composite video signal, and synchronization signals extracted therefrom, are recorded in spatial registry on separate channels of a longitudinal tape recorder/reproducer. Vertical synchronization quality is maintained by recording on a channel capable of low frequency processing. Upon reproduction all synchronization, including mixing with supplemental video sources, is synchronized to the recorded master video synchronization and blanking signals. Video display at other than normal speeds is temporally synchronized from the slower tape speed. An X-Y monitor driven by vertical and horizontal sweep signals synchronized to the corresponding recorded synchronization signals generates a video presentation without repeated or omitted frames.
    Type: Grant
    Filed: April 7, 1981
    Date of Patent: March 22, 1983
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Gilbert G. Kuperman, Donald E. Lewis