Abstract: An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.

Abstract: A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: A data processing apparatus and a method of indicating operation of a data processor within a secure domain. The apparatus comprising a display for displaying data; a processor operable in a secure domain, said processor when operating in said secure domain having access to a user specific image; wherein said processor is operable to indicate operation within said secure domain by displaying said user specific image on at least a portion of said display when operating within said secure domain.

Abstract: A data processing device is provided with a processor core 8 that can operate in either a secure domain or a non-secure domain. Data stored within a secure region 34 of a memory 10 can only be accessed when the processor core 8 is executing in the secure domain. A frame buffer 36 for storing a display image 20 to be displayed is stored within a non-secure region of memory which can be accessed by the processor core 8 irrespective of whether it is in the secure domain or the non-secure domain as well as a display controller 12. When a subject image 22 is written to the frame buffer 36, validation data for the subject image 22 is stored within the secure region 34. When a user input is received the displayed data stored at a validated display area to which the subject image was written is read back and used to generate check data with is compared with the validation data before the user input is authenticated.

Abstract: A handheld device 300 generates a verification image to indicate that the device is operating in a secure domain. The verification image is generated in dependence upon secure data stored within a secure region 324 of a memory 310 and user input data captured from a user input device 314, 316, 320. The secure data may be data defining a three-dimensional object. The user image data may be captured from accelerometers 314 defining a viewpoint of the secret three-dimensional object.

Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des

Abstract: A data processing apparatus is configured to perform secure data processing operations and non-secure data processing operations, wherein the apparatus includes a master device with a secure domain and a non-secure domain. Components of the master device operate in the secure domain when performing secure data processing operations and operate in the non-secure domain when performing the non-secure data processing operations. A slave device is configured to perform a delegated data processing operation specified by the master device and a communication bus connecting the master device to the slave device. The delegated operation is initiated by an issuing component in the master device, wherein the slave device includes a security inheritance mechanism configured to cause the delegated operation to inherit a non-secure security status or a secure status depending upon whether the issuing component in the master device is operating in the non-secure domain or the secure domain.

Abstract: An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.

Abstract: A data processor for processing data in a secure mode having access to secure data that is not accessible to the data processor when processing data in the non-secure mode. A further processing device for performing a task in response to a request from the data processor issued from the non-secure mode. The further processing device including a secure data store not accessible to processes running on the data processor when in the non-secure mode. Prior to issuing requests, the data processor in the secure mode performs a set up operation on the further data processing device storing secure data in the secure data store. In response to receipt of the request from the data processor operating in the non-secure mode, the further data processing device performs the task using data stored in the secure data store to access any secure data required.

Abstract: A data processing device is provided with a processor core 8 that can operate in either a secure domain or a non-secure domain. Data stored within a secure region 34 of a memory 10 can only be accessed when the processor core 8 is executing in the secure domain. A frame buffer 36 for storing a display image 20 to be displayed is stored within a non-secure region of memory which can be accessed by the processor core 8 irrespective of whether it is in the secure domain or the non-secure domain as well as a display controller 12. When a subject image 22 is written to the frame buffer 36, validation data for the subject image 22 is stored within the secure region 34. When a user input is received the displayed data stored at a validated display area to which the subject image was written is read back and used to generate check data with is compared with the validation data before the user input is authenticated.

Abstract: A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated therewith. The control data controls access to the cached data. Program instructions executed by the processors 4, 6 control a cache controller 26 to modify the control data associated with the cached data while it remains stored within the cache memory 14 and remains valid. The control data may, for example, specify a security flags indicating whether access is restricted to secure processes or processors.

Abstract: A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable to perform at least part of the process on behalf of the main processing logic. A memory is provided that is accessible by the main processing logic when performing the process, the main processing logic defining a portion of the memory to be allocated memory accessible to the subsidiary processing logic when performing part of the process on behalf of the main processing logic. Further, a memory management unit is provided that is programmable by the main processing logic and operable to control access to the allocated memory by the subsidiary processing logic.

Abstract: A handheld device 300 generates a verification image to indicate that the device is operating in a secure domain. The verification image is generated in dependence upon secure data stored within a secure region 324 of a memory 310 and user input data captured from a user input device 314, 316, 320. The secure data may be data defining a three-dimensional object. The user image data may be captured from accelerometers 314 defining a viewpoint of the secret three-dimensional object.

Abstract: Test access to an integrated circuit 2 is controlled by the use of test access enabling keys. A plurality of different test access enabling levels may be supported corresponding to different keys. The test access control may be performed by dedicated hardware or software executing a secure privilege mode.

Abstract: A data processing apparatus comprising a data processor for processing data in a secure and a non-secure mode, said data processor processing data in said secure mode having access to secure data that is not accessible to said data processor processing data in said non-secure mode; and a further processing device for performing a task in response to a request from said data processor issued from said non-secure mode, said task comprising processing data at least some of which is secure data, said further processing device comprising a secure data store, said secure data store not being accessible to processes running on said data processor in non-secure mode; wherein prior to issuing any of said requests said data processor is adapted to perform a set up operation on said further data processing device, said set up operation being performed by said data processor operating in said secure mode and comprising storing secure data in said secure data store on said further processing device, said secure data being

Abstract: A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated therewith. The control data controls access to the cached data. Program instructions executed by the processors 4, 6 control a cache controller 26 to modify the control data associated with the cached data whilst it remains stored within the cache memory 14 and remains valid. The control data may, for example, specify a security flags indicating whether access is restricted to secure processes or processors.

Abstract: A data processing apparatus and method are provided for managing access to content within the data processing apparatus. The data processing apparatus has a secure domain and a non-secure domain and comprises at least one device which is operable when seeking to access content stored in memory to issue a memory access request pertaining to either the secure domain or the non-secure domain. Further, writeable memory is provided which can store content required by the at least one device, with the writeable memory having at least one read only region whose content is stored therein under control of a secure task, the secure task being a task executed by one of the devices in the secure domain.

Abstract: Test access to an integrated circuit 2 is controlled by the use of test access enabling keys. A plurality of different test access enabling levels may be supported corresponding to different keys. The test access control may be performed by dedicated hardware or software executing a secure privilege mode.

Abstract: A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable to perform at least part of the process on behalf of the main processing logic. A memory is provided that is accessible by the main processing logic when performing the process, the main processing logic defining a portion of the memory to be allocated memory accessible to the subsidiary processing logic when performing part of the process on behalf of the main processing logic. Further, a memory management unit is provided that is programmable by the main processing logic and operable to control access to the allocated memory by the subsidiary processing logic.