Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage.

Abstract: A semiconductor memory device sensing circuit (400) is disclosed. The circuit includes a number of sense amplifiers (402), each of which is coupled to a first supply node (414) by a first driver device (P404-0 to P404-n), and to a second supply node (420) by a second driver device (N404-0 to N404-n). An increased driving current capability is provided by a number of first boost capacitors (C400) coupled between the first supply node (414) and an intermediate voltage (Vplate), and a number of second boost capacitors (C402) coupled between the second supply node (420) and the intermediate voltage (Vplate).

Abstract: A memory array (10) implemented by an integrated circuit is provided. The memory array (10) includes a bank of standard array cells (12) arranged in rows and columns. The bank of standard array cells (12) includes a plurality of rows of array cells (14) operable to provide memory storage and a plurality of rows of dummy cells (16) operable to provide a reference voltage level. A row decode block (22) is coupled to the bank of standard array cells via a plurality of wordlines (18) which include array cell wordlines and dummy cell wordlines. A sense amplifier block (24) is coupled to the bank of standard array cells (12) via a plurality of bitlines (20). The sense amplifier block (24) includes a plurality of sense amplifiers (26) coupled to the bitlines.

Abstract: An apparatus for assuring vertical alignment of visual axes of a patient's eyes includes an eye cup that enables establishment of a liquid bath in which a surface of a cornea of a supine patient's first eye is completely submerged. A first light source is positioned above the liquid bath and directs a beam of alignment light to the submerged eye. A second light source is positioned above the patient's second eye and directs a beam of adjustment light to its corneal surface. Apparatus is provided that enables relative movement between the first and second light sources so as to enable the light sources to be moved into a position where the patient indicates a fusion of the light sources into a single spot, at which point it is known that the visual axis are vertical and aligned. The liquid bath assures that the beam of alignment light from the first light source is only in focus at the patient's eye when the first light source is directly coincident with the vertical axis of the first eye.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: An ultrasonic biometer images an eye structure and enables measurement of a cornea's thickness at various points about the cornea's surface curvature. The biometer employs a liquid bath in contact with the corneal surface and includes a curved track positioned above the liquid bath, the curved track having a path that closely approximates the surface curvature of the corneal surface. An ultrasonic transducer (having a central axis) is movably mounted by a connector structure along the track and is positioned in communication with the liquid bath. The connector structure operates to maintain the central axis of the ultrasonic transducer perpendicular to a tangent drawn to the curved track, at a plurality of locations along the track. When the connector structure is moved along the curved track, it enables an ultrasonic beam, generated by the transducer, to interrogate areas of the corneal surface, with the angle of incidence of the beam being substantially orthogonal to the surface.

Abstract: An ultrasound system that enables determination of layer thicknesses and contours of a multi-layer organic body includes a transmitter/receiver for obtaining a radio frequency signal from echoes over a plurality of points on the organic surface. Each radio frequency signal is then deconvolved to remove apparatus generated noise and filtered to create an analytic signal that exhibits a magnitude related to an instantaneous rate of arrival of total echo energy received by the transmitter/receiver. Analytic signals from adjacent parallel scans are then cross-correlated and magnitude detected to determine energy peaks to enable accurate determination of echo producing surfaces of each layer of the multi-layer organic body across the plurality of interrogation points. In the application of the invention to Corneal Epithelium Mapping, a pupil monitoring system is included that disables the measurement system if the pupil's gaze wanders so as to cause a diversion of the optical axis.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A method is provided for forming multiple layers of interconnections adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: A memory cell (10) comprises a ferromagnetic gate (12) disposed above a source (18) and a drain (20) in a substrate (16). A magnetic field is created in the ferromagnetic gate (12) by producing a large current between the source (18 ) and drain (20). The orientation of the magnetic field will depend upon the direction of the current flow. To read information from the memory cell (10), a small current is passed from source (18) to drain (20); if the electrons (25) are deflected upwards towards the surface (24) of the substrate (16), a lesser current will result than if the electrons (25) are deflected downward towards the bottom of the channel (22). Hence, the magnetic orientation, and therefore the information stored within the memory cell (10), can be determined by the amount of current detected.

Abstract: A switch including a plunger adapted for reciprocal motion in a housing. A substantially rigid first wiper is fixedly mounted to a cam for selective rotation in the housing. One end of the plunger engages the cam for altering the position of the first wiper relative to an electrical contact. The first wiper and electrical contact are arranged to define a make-before-break switching action. A cam follower provides a detent action of the cam which facilitates high speed switching independent of the actuation speed of the plunger. A second wiper is interposed between opposed ends of the plunger and selectively actuates a flash-to-pass feature.

Abstract: Hydrogen annealing permits deposition of good quality polysilicon atop TiO.sub.2. Hydrogen annealing of TiO.sub.2 prevents the tremendous hydrogen affinity of as-deposited TiO.sub.2 from disrupting process reactions during deposition of polysilicon.

Abstract: An electric dry shaver having a movable long hair clipper which is slidable from a retracted position within the shaver housing to an extended position in which the clipping teeth of the clipper are exposed. The clipper includes a relatively fixed blade or comb supported by a molded plastic part which performs the functions of guiding the movable clipper, providing a detent action for the movable clipper and interconnecting the clipper assembly with a manually actuable member which extends through the wall of the shaving housing. The shaver also includes a roller supported between a pair of shaving heads by the means for tensioning the flexible comb on its supporting frame.

Abstract: An electric dry shaver having a movable long hair clipper which is slidable from a retracted position within the shaver housing to an extended position in which the clipping teeth of the clipper are exposed. The clipper includes a relatively fixed blade or comb supported by a molded plastic part which performs the functions of guiding the movable clipper, providing a detent action for the movable clipper and interconnecting the clipper assembly with a manually actuable member which extends through the wall of the shaving housing. The shaver also includes a roller supported between a pair of shaving heads by the means for tensioning the flexible comb on its supporting frame.