Patents by Inventor Donald L. Faw
Donald L. Faw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220334963Abstract: Examples described herein relate to circuitry, when operational, configured to: store records of memory accesses to a memory device by at least one requester based on a configuration, wherein the configuration is to specify a duration of memory access capture. In some examples, the at least one requester comprises one or more workloads running on one or more processors. In some examples, the configuration is to specify collection of one or more of: physical address ranges or read or write access type.Type: ApplicationFiled: June 24, 2022Publication date: October 20, 2022Inventors: Ankit PATEL, Lidia WARNES, Donald L. FAW, Bassam N. COURY, Douglas CARRIGAN, Hugh WILKINSON, Ananthan AYYASAMY, Michael F. FALLON
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Patent number: 11290392Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.Type: GrantFiled: June 12, 2017Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Sujoy Sen, Mohan J. Kumar, Donald L. Faw, Susanne M. Balle, Narayan Ranganathan
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Publication number: 20210019069Abstract: Examples herein relate to a system capable of coupling to a remote memory pool, the system comprising: a memory controller and an interface to a connection, the interface coupled to the memory controller. In some examples, the interface is to translate a format of a memory access request to a format accepted by the memory controller and the memory controller is to provide the translated memory access request in a format accepted by a media. In some examples, a controller is to measure a number of addressable regions that are least accessed and cause at least one of the least accessed regions to be evicted to a local or remote memory device with relatively higher latency.Type: ApplicationFiled: September 24, 2020Publication date: January 21, 2021Inventors: Sujoy SEN, Thomas E. WILLIS, Durgesh SRIVASTAVA, Marcelo CINTRA, Bassam N. COURY, Donald L. FAW, Francois DUGAST
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Publication number: 20180219797Abstract: Technologies for pooling accelerators over fabric are disclosed. In the illustrative embodiment, an application may access an accelerator device over an application programming interface (API) and the API can access an accelerator device that is either local or a remote accelerator device that is located on a remote accelerator sled over a network fabric. The API may employ a send queue and a receive queue to send and receive command capsules to and from the accelerator sled.Type: ApplicationFiled: June 12, 2017Publication date: August 2, 2018Inventors: Sujoy Sen, Mohan J. Kumar, Donald L. Faw, Susanne M. Balle, Narayan Ranganathan
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Patent number: 9904027Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: GrantFiled: December 14, 2016Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Donald L. Faw, Uri V. Cummings, Terrence J. Trausch, Daniel P. Daly, Andrew C. Alduino
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Publication number: 20170102510Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 14, 2016Publication date: April 13, 2017Inventors: Donald L. FAW, Uri V. CUMMINGS, Terrence J. TRAUSCH, Daniel P. DALY, Andrew C. ALDUINO
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Patent number: 9609782Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: GrantFiled: January 15, 2014Date of Patent: March 28, 2017Assignee: INTEL CORPORATIONInventors: Donald L. Faw, Uri V. Cummings, Terrence J. Trausch, Daniel P. Daly, Andrew C. Alduino
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Publication number: 20150334867Abstract: Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may comprise a plurality of sleds with individual sleds including one or more compute nodes; and a networking element coupled with a sled of the plurality of sleds and configured to communicatively connect the sled to one or more other components of the rack assembly via an optical communication system. The optical communication system may include an external optical cable configured to communicatively connect the networking element with the rack assembly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 15, 2014Publication date: November 19, 2015Inventors: Donald L. FAW, Uri V. CUMMINGS, Terrence J. TRAUSCH, Daniel P. DALY, Andrew C. ALDUINO
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Patent number: 8907737Abstract: Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.Type: GrantFiled: December 28, 2012Date of Patent: December 9, 2014Assignee: Intel CorporationInventors: Harry Muljono, Donald L. Faw, Charlie Lin, Stefan Rusu
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Publication number: 20140184349Abstract: Techniques and mechanisms for configuring logic to implement a signal modulation. In an embodiment, the logic includes a finite impulse response (FIR) module comprising circuitry. The selection circuitry may be operable to concurrently receive signals from latch circuitry of the FIR module and, based on the signals, to select an input group of the selection circuitry and to output a voltage identifier. In another embodiment, configuration logic is operable to set an operational mode which determines a total number of concurrent input signals, received by the FIR module, which the FIR module will use to select an input group for generating an output representing a voltage level.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Inventors: Harry Muljono, Donald L. Faw, Charlie Lin, Stefan Rusu
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Patent number: 7596650Abstract: In one embodiment, the present invention includes an apparatus having a first interface to process data for communication according to at least first and second protocols, a second interface to process data for communication according to at least the first and second protocols, and a common buffer coupled to the first and second interfaces to temporarily store the data. In another embodiment, a passive interposer includes at least one interconnect. The passive interposer can be coupled to an unpopulated socket of a system to route signals from a first processor to a device coupled to the unpopulated socket. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2006Date of Patent: September 29, 2009Assignee: Intel CorporationInventors: Vikas Aditya, Donald L. Faw