Patents by Inventor Donald L. Wollesen

Donald L. Wollesen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6150693
    Abstract: A field effect transistor (FET) with a V-shaped trench gate in a semiconductor substrate having gate oxide on the walls of the trench and a gate electrode material within the trench walls, and source/drain impurities in the semiconductor substrate and abutting the gate oxide. The resultant FET structure comprises a non-self align V-shaped gate with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Because of the V-shaped structure of the gate, the effective length of the channel only extends from the edge of the source to the tip of the V-shaped gate. Due to this characteristic, the width of the gate at the surface of the semiconductor substrate can be two or more time the distance of the desired channel length thereby permitting conventional lithography to be used to fabricate gate lengths much shorter than the lithography limit. Preferably, the bottom or tip of the V shaped gate is rounded and concave.
    Type: Grant
    Filed: May 12, 1998
    Date of Patent: November 21, 2000
    Assignee: Advanced Micro Devices
    Inventor: Donald L. Wollesen
  • Patent number: 6146985
    Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: November 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald L. Wollesen
  • Patent number: 6147378
    Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: November 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 6140186
    Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: October 31, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Ren Lin, Peng Fang, Donald L. Wollesen
  • Patent number: 6124608
    Abstract: A non-volatile memory device having a trench structure and a shallow drain region is formed in a substrate, thereby facilitating increased densification, improved planarization and low power programming and erasing. Embodiments include forming first and second trenches in a substrate and, in each trench, sequentially forming a substantially U-shaped tunnel dielectric layer and a substantially U-shaped floating gate electrode. A dielectric layer is then formed on the floating gate electrode extending on the substrate surface and a substantially T-shaped control gate electrode is formed filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form a shallow drain region between the first and second trenches and source regions extending to a greater depth than the drain region.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang William Liu, Yu Sun, Donald L. Wollesen
  • Patent number: 6097061
    Abstract: A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region, a drain region, and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: August 1, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 6093331
    Abstract: A method for the precise removal of the backside silicon on face down semiconductor devices to obtain a planar surface to allow electron beam microprobe analysis of the semiconductor device. The backside silicon is removed by plasma etching in a fluorocarbon based chemical plasma. The epitaxial layer in a CMOS device acts as an etch stop and the buried oxide layer in an SOI device acts as an etch stop.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: July 25, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald L. Wollesen
  • Patent number: 6002151
    Abstract: A non-volatile memory device is formed in a substrate, thereby enabling increased densification. Embodiments include forming a trench in a substrate, forming a substantially U-shaped tunnel dielectric layer in the trench, depositing a substantially U-shaped floating gate electrode on the tunnel dielectric layer, forming a dielectric layer on the floating gate electrode extending on the substrate surface and forming a substantially T-shaped control gate electrode filling the trench and extending on the substrate. Sidewall spacers are formed on side surfaces of the control gate electrode and dielectric layer, followed by ion implantation to form source/drain regions extending into the substrate to substantially the same depth, leaving a region containing an impurity of the first conductivity type at the intersection of the trench and substrate surface which prevents shorting between the source/drain region and gate electrodes.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 14, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang William Liu, Yu Sun, Donald L. Wollesen
  • Patent number: 5999465
    Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of producing a light pulse having a light pulse energy, applying the light pulse to the device at a predetermined location, varying the light pulse energy, and detecting soft errors in the device. In another embodiment, the apparatus includes a light source for producing a light pulse that is applied to the device at a predetermined location, a light pulse energy varying circuit coupled to the light source and configured to vary the light energy of the light pulse, and a detecting circuit coupled to the device and configured to detecting soft errors in the device.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: December 7, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil Narayan Shabde, Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 5991134
    Abstract: An electrostatic discharge protection circuit having a low impedance conduction path connecting all of a particular device's input/output paths to ground potential via switchable devices exhibiting low resistance when power is not applied to the device and very high resistance when power is applied to the device.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: November 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Huynh Tan, Donald L. Wollesen
  • Patent number: 5990515
    Abstract: A non-volatile semiconductor cell structure and method comprises a trenched floating gate, a sidewall doping and a corner doping and further includes a sidewall doped region, a corner doped region, a channel region, and an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate. In a preferred embodiment, the trenched floating gate has a top surface which is substantially planar with a top surface of the semiconductor substrate. The control gate and the inter-gate dielectric are formed on the top surface of the trenched floating gate. The sidewall doped region and the corner doped region are laterally separated by the trench in which the trenched floating gate is formed. The sidewall doped region has a depth which is greater than the depth of the trench, and the corner doped region has a depth which is less than the depth of the trench.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: November 23, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 5982691
    Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes by measuring the charge Q.sub.c that flow through a node of an equivalent diode structure when the diode structure is impinged by a light pulse with energy equivalent to that of the alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of producing a light pulse having a light pulse energy, the light pulse energy is at a first light pulse energy; applying the light pulse to the device at a predetermined location, the predetermined location having an area and a geometry; varying the light pulse energy to a second light pulse energy which generates a soft error; detecting soft errors in the device; providing a diode having the same area and geometry as the predetermined location; applying the light pulse with the second light pulse energy to the diode; and determining the amount of charges that flow through the diode.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: November 9, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil Narayan Shabde, Donald L. Wollesen
  • Patent number: 5972725
    Abstract: A method of precisely measuring electrical parameters in integrated circuits in a face down semiconductor device in which a portion of the semiconductor substrate is removed from the semiconductor device and an SEM microprobe is directed onto selected regions of the surface exposed by the removal of the semiconductor substrate. The microprobe is directed to selected regions of the exposed surface by a computer generated mapping system. One of the selected regions that the microprobe is directed to is a region of the exposed surface overlying a depletion region associated with a drain of a transistor in the semiconductor device. The voltage variation on the exposed surface caused by the expansion and shrinking of the depletion region is measured by the microprobe. Another region that the microprobe is directed to is a region of the exposed surface overlying an insulator and the microprobe detects the voltage of a conducting electrode under the insulator is measured via capacitive coupling.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: October 26, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Donald L. Wollesen, Glen Gilfeather
  • Patent number: 5960271
    Abstract: A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: September 28, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Donald L. Wollesen, Homi Fatemi
  • Patent number: 5923063
    Abstract: Floating gates of nonvolatile memory cells are formed in pairs within a pyramidal or truncated pyramidal opening in a semiconductor layer between a top surface thereof and a heavily doped source region spaced from the surface of the semiconductor layer. The floating gates control the conductance of channel regions formed along the sloped sidewalls of the pyramidal openings between surface drains and the buried source region.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: July 13, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen, John T. Yue
  • Patent number: 5904528
    Abstract: Asymmetrically doped source/drain regions of a transistor are formed employing protective insulating layers to prevent a portion of the gate electrode from receiving an excessive impurity implantation dose and penetrating through the underlying gate insulating layer into the semiconductor substrate. Sidewall spacers are employed during heavy implantation.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: May 18, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ming-Ren Lin, Peng Fang, Donald L. Wollesen
  • Patent number: 5900668
    Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: May 4, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald L. Wollesen
  • Patent number: 5877667
    Abstract: Various embodiments of on chip-transformers constructed in separate metal layers in an insulator that serves as a dielectric which is formed on a substrate such as a silicon substrate. Windings with currents flowing in a first direction are constructed in a first metal layer and windings with currents flowing a second direction are constructed in a second metal layer. Windings in the first metal layer are connected to windings in the second metal layer by connectors such as vias. The transformer can be constructed in a balun layout, an autotransformer layout, a layout with the secondary separated from the primary, a layout with the secondary separated the primary and rotated with respect to an axis of the primary, a layout in which the transformer is a two stage transformer and with the first stage constructed orthogonal to the second stage, or a transformer in which the windings are constructed in a toroidal layout.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: March 2, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald L. Wollesen
  • Patent number: 5864158
    Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: January 26, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yowjuang W. Liu, Donald L. Wollesen
  • Patent number: 5856708
    Abstract: A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: January 5, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Donald L. Wollesen